Switching activity

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http://vlsisystemdesign.com/switchAct.php

A CMOS, is basically an inverter logic (NOT gate), that consists of a PMOS at the top, and NMOS at the bottom (as shown in figure below), whose 'gate' and 'drain' terminal are tied together. The 'gate' terminals of both the MOS transistors is the input side of an inverter, whereas, the 'drain' terminals form the output side.

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Switching activity

  1. 1. Now we have understood, For any signal to be considered as logic ‘0’ and logic ‘1’, it should be in the NML and NMH ranges, respectively3/2/2013 1
  2. 2. Now we have understood, For any signal to be considered as logic ‘0’ and logic ‘1’, it should be in the NML and NMH ranges, respectively Now, let us understand the factors affecting the voltage levels to vary from this range3/2/2013 2
  3. 3. Ideal Switching Activity Actual Switching ActivitySwitching Activity of a Device is one of the factors which affects the voltage levels ofInput/Output signals
  4. 4. Vdd Poly Gate PMOS – P Diff In Out NMOS – N Diff VssLets understand the internal process while Switching Activity happens in a Device
  5. 5. Vdd Poly Gate PMOS – P Diff In Out NMOS – N Diff Vss PMOS NMOSConsider the MOS device, to understand the actual scenario
  6. 6. PMOS NMOS Let’s revise MOS device characteristics
  7. 7. MOS device characteristics
  8. 8. MOS device characteristics
  9. 9. MOS device characteristics
  10. 10. MOS device characteristics
  11. 11. MOS device characteristics
  12. 12. MOS device characteristics
  13. 13. MOS device characteristics
  14. 14. MOS device characteristics
  15. 15. MOS device characteristics
  16. 16. MOS device characteristics
  17. 17. MOS device characteristics G Vgs S D NMOS Vgs is the Voltage between gate and source
  18. 18. MOS device characteristics G VgsS D NMOS
  19. 19. MOS device characteristics G Vgs Vgs < VT (Threshold Voltage) S DS D NMOS If Vgs is less then VT , the NMOS will act as Open Switch
  20. 20. MOS device characteristics G Vgs Vgs > VT (Threshold Voltage) S DS D NMOS If Vgs is greater then VT , the NMOS will act as Closed Switch
  21. 21. MOS device characteristics G Vgs Vgs > VT S DS D NMOS
  22. 22. MOS device characteristics G Vgs Vgs > VT S DS D NMOS When MOSFET is ‘ON’, it can be modeled as a ‘Resistor’ with switch closed
  23. 23. MOS device characteristics G Vgs Vgs > VT S DS D NMOS When MOSFET is ‘ON’, it can be modeled as a ‘Resistor’ with switch closed When MOSFET is ‘OFF’, it can be modeled as an ‘open switch’
  24. 24. When MOSFET is ‘ON’, it can be modeled as a ‘Resistor’ with closed switch
  25. 25. When MOSFET is ‘ON’, it can be modeled as a ‘Resistor’ with switch closedPMOS acts as Logic ‘0’ NMOS acts as Logic ‘1’
  26. 26. When MOSFET is ‘ON’, it can be modeled as a ‘Resistor’ with switch closedPMOS acts as Logic ‘0’ NMOS acts as Logic ‘1’When MOSFET is ‘OFF’, it can be modeled as an ‘open switch’
  27. 27. When MOSFET is ‘ON’, it can be modeled as a ‘Resistor’ with switch closed PMOS acts as Logic ‘0’ NMOS acts as Logic ‘1’ When MOSFET is ‘OFF’, it can be modeled as an ‘open switch’ PMOS NMOSPMOS acts as Logic ‘1’ NMOS acts as Logic ‘0’
  28. 28. VddIn Out Vss Input Switching from logic ‘1’ to logic ‘0’
  29. 29. VddIn Out Vss Input Switching from logic ‘1’ to logic ‘0’ NMOS is turning ‘OFF’
  30. 30. VddIn Out Vss Input Switching from logic ‘1’ to logic ‘0’ NMOS is turning ‘OFF’ PMOS is turning ‘ON’
  31. 31. Input Switching from logic ‘1’ to logic ‘0’
  32. 32. Input Switching from logic ‘1’ to logic ‘0’NMOS is turning ‘OFF’
  33. 33. Input Switching from logic ‘1’ to logic ‘0’NMOS is turning ‘OFF’PMOS is turning ‘ON’
  34. 34. Input Switching from logic ‘1’ to logic ‘0’ NMOS is turning ‘OFF’ PMOS is turning ‘ON’ VddIn Out Vss
  35. 35. Input Switching from logic ‘1’ to logic ‘0’ NMOS is turning ‘OFF’ PMOS is turning ‘ON’ Vdd Vdd RIn Out Out Vss Vss Replace PMOS as resistor and NMOS by open switch.
  36. 36. Input Switching from logic ‘1’ to logic ‘0’ NMOS is turning ‘OFF’ PMOS is turning ‘ON’ Vdd Vdd R R Out Out CL Vss VssConnect Capacitor on output end.
  37. 37. Input Switching from logic ‘1’ to logic ‘0’ NMOS is turning ‘OFF’ PMOS is turning ‘ON’ Vdd R Out CL VssConsider Capacitor is charged when Vdd is applied.
  38. 38. Input Switching from logic ‘1’ to logic ‘0’ NMOS is turning ‘OFF’ PMOS is turning ‘ON’ Vdd R Out CL VssConsider Capacitor is charged up to Vdd
  39. 39. Input Switching from logic ‘1’ to logic ‘0’ NMOS is turning ‘OFF’ PMOS is turning ‘ON’ VddR Out CL Vss
  40. 40. Summary Vdd Vdd RIn Out Out CL Vss Vss
  41. 41. Summary Vdd R Out CL VssLets convert the area within dotted lines into closed loop circuit.
  42. 42. Summary Vdd R R OutVdd CL CL Vss Lets convert into closed loop circuit.
  43. 43. Summary Vdd R R OutVdd CL CL Vss Lets convert into closed loop circuit.
  44. 44. Summary Capacitor Models RVdd CL
  45. 45. Summary Capacitor Models R Uncharged Cap + 0V short -Vdd CL + + Charged Cap V VO - O - + Fully Charged Cap Open circuit -
  46. 46. Summary Waveforms RVdd CL
  47. 47. Summary Waveforms Vdd RVdd CL
  48. 48. Summary Waveforms Vdd R VCLVdd CL
  49. 49. Summary Waveforms Vdd R VCLVdd CL VR
  50. 50. Summary Waveforms Vdd R VCLVdd CL VR I = V/R
  51. 51. Summary Waveforms Vdd R VCLVdd CL VR I = V/R IR
  52. 52. Summary Waveforms Vdd R VCLVdd CL VR I = V/R Ipeak IR
  53. 53. So what can we conclude!!!
  54. 54. So what can we conclude!!!A capacitor needs at least Ipeak amount of current
  55. 55. So what can we conclude!!!A capacitor needs at least Ipeak amount of currentIpeak IR
  56. 56. So what can we conclude!!!A capacitor needs at least Ipeak amount of currentIpeak IR To get charged upto Vdd voltage
  57. 57. So what can we conclude!!!A capacitor needs at least Ipeak amount of currentIpeak IR To get charged upto Vdd voltage VCL
  58. 58. So what can we conclude!!!A capacitor needs at least Ipeak amount of currentIpeak IR To get charged upto Vdd voltage VCLAnd, the output of inverter, is recognized as logic ‘1’
  59. 59. So what can we conclude!!!A capacitor needs at least Ipeak amount of currentIpeak IR To get charged upto Vdd voltage VCLAnd, the output of inverter, is recognized as logic ‘1’
  60. 60. And, the output of inverter, is recognized as logic ‘1’
  61. 61. And, the output of inverter, is recognised as logic ‘1’ What does this mean????
  62. 62. And, the output of inverter, is recognised as logic ‘1’ What does this mean???? It means that the voltage across capacitor Vpeak VCL
  63. 63. And, the output of inverter, is recognised as logic ‘1’ What does this mean???? It means that the voltage across capacitor Vpeak VCL Lies in NMH level of noise margin graph
  64. 64. VddVOH NMHVIH Noise Margin High NMH = VOH - VIH NML = VIL - VOLVIL NML Noise Margin HighVOL 0
  65. 65. Why to do?3/2/2013 65

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