The Universal Asynchronous Receiver/Transmitter (UART) controller is the key component of the serial communications subsystem of a computer. The UART takes bytes of data and transmits the individual bits in a sequential fashion. At the destination, a second UART re-assembles the bits into complete bytes.

1. FPGA
IMPLEMENTATION
OF
UART CONTROLLER
By:-
JIGYASA POPAT
SUBHANKAR KOLAY
VARUN KAMBRATH

2. CONTENTS
 Introduction to the universal asynchronous
receiver transmitter : UART
 UART software implementation.
 UART hardware implementation on FPGA
 Initialize the UART Hardware
 UART controls using real term hyper terminal.

3. INTRODUCTION
 Parallel communication implies sending a whole byte (or
more) of data over multiple parallel wires
 Serial communication implies sending data bit by bit over
a single wire
 There are 2 types of serial communication:
I. Asynchronous
II. Synchronous

4. U A R T
 Universal Asynchronous Receiver Transmitter
 Asynchronous transmission means a data (including one
start bit, 8-bit data, and stop bits) can be sent at any
time.
 RS-232 is a serial communication standard.
 Since it is asynchronous, no external clock is needed, only
3 wires are required for the simplest RS-232 connection
GND, TX(transmit) and RX(receive).

5. U A R T
• Start Bit- Indicates the beginning of the Data word
• Stop Bit- Indicates the end of the Data word
• Parity Bit- Added for error detection (optional)
• Data Bit- The actual data to be transmitted
• Baud Rate- The bit rate of the serial port
• Throughput- Actual data transmitted per second (total bits
transmitted overhead
 Eg: 9600 baud = 9600 bits/sec
 If using 8data bits, 1start, 1stop & no parity, effective
throughput is 9600 *8/10 = 7680 bits/sec

6. TX & RX

7. U A R T
• Asynchronous transmission is easy to implement but less
efficient as it requires extra 2-3 control bits for every 8
data bits
• This method is usually used for low volume & long
distance communication.

8. FLOWCHART

9. FLOWCHART

10. CYCLONE II DE1

11. Tech Specs
512 kB SRAM
10 Toggle switches 4 Push Button switches
4 MB Flash
Memory
8 MB SDRAM
10 RED LED’s 8 GREEN LED’s
Oscillator –
50 MHz, 27 MHz
40 pin
Expansion
headers
RS-232
Transceiver
FPGA
VGA out

12. OPERATION
• Joint Test Action Group (JTAG)
I. The configuration data is directly loaded into the FPGA
II. Used for simple testing digital circuits
III. The configuration remains loaded as long as the power is ON
• Active Serial (AS)
I. The configuration data is loaded into the Flash memory
II. The configuration is not lost when the power is turned OFF
III. Used after the digital circuit is verified

13. HYPER-TERMINAL
• Real Term Hyper-terminal is used at PC’s as virtual terminal
• It needs to be configured to 9600 bauds, 1 stop bit, no
parity
• Both Character and ASCII code are displayed
• Compatible with Windows 7,8

14. REFERENCE
1. FPGA Implementation of Universal Asynchronous Receiver
and Transmitter (UART) by Haibo Wang
2. Synthesis and Implementation of UART using VHDL Codes
- 2012 International Symposium on Computer, Consumer
and Control, Dr. Garima Bandhawarkar Wakhle
3. VHDL A primer – J Bhaskar
4. www.altera.com
5. www.wikipedia.org