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  1. 1. POWER Introduction to Low Power VLSI Design Dr Anu Mehra
  2. 2. Where Does Power Go in CMOS?
  3. 3. <ul><li>Power dissipation can be </li></ul><ul><li>dynamic </li></ul><ul><ul><li>due to capacitive switching </li></ul></ul><ul><ul><li>short circuit power due to crowbar currents </li></ul></ul><ul><ul><li>Glitches in output waveform </li></ul></ul><ul><li>Static </li></ul><ul><ul><li>leakage currents – </li></ul></ul><ul><ul><li>sub threshold current + reverse bias </li></ul></ul><ul><ul><li>standby current –pseudo nmos </li></ul></ul>
  4. 4. Dynamic Power Charging and discharging of capacitors due to logic switching event
  5. 5. <ul><li>Each time the input switches from 0to 1 or 1 to 0 power is consumed. </li></ul><ul><li>PART IS DISSPATED in charging and discharging the capacitor </li></ul><ul><li>PART IS STORED in the load capacitor </li></ul>
  6. 6. Dynamic Power Dissipation Energy/transition = C L * V dd 2 Power = Energy/transition * f = C L * V dd 2 * f 0 to1 or 1 to 0 Need to reduce C L , V dd , and f to reduce power. Not a function of transistor sizes! i VDD f 0 to1 or 1 to 0 is the frequency of transition Vin Vout C L Vdd
  7. 7. Half the energy stored in the Capacitor, the other half is lost !
  8. 8. Node Transition Activity and Power
  9. 9. Transistor Sizing for Minimum Energy <ul><li>A quick review of delay </li></ul>
  10. 10. Delay Formula C int =  C gin with   1 f = C ext /C gin - effective fanout C ext =fC gin R = R unit /W ; C int =WC unit t p 0 = 0.69 R unit C unit Let tp=0.69 Req(Cint+Cext) =0.69 ReqCint(1+Cext/Cint) =tp0(1+Cext/Cint) =tp0(1+f/  )
  11. 11. Transistor Sizing for Minimum Energy <ul><li>Goal: Minimize Energy of whole circuit </li></ul><ul><ul><li>Design parameters: f and V DD </li></ul></ul><ul><ul><li>tp  tpref of circuit with f =1 and V DD =V ref </li></ul></ul>
  12. 12. Delay as a function of V DD
  13. 13. <ul><li>Total Capacitance of inverter chain is </li></ul><ul><li>Cg1+Cint1+Cext1+Cint2+Cext2 </li></ul><ul><li>=Cg1+  Cg1+fCg1+f  Cg1+FCg1 </li></ul><ul><li>=Cg1(1+  f  f  F) </li></ul><ul><li>E=V DD 2 (total capacitance) </li></ul>
  14. 14. Transistor Sizing (2) <ul><li>Performance Constraint (  =1) </li></ul><ul><li>Energy for single Transition </li></ul>
  15. 15. Let for a reference device f=1
  16. 17. Transistor Sizing (3) F =1 2 5 10 20 V DD = f (f) E/E ref = f (f)
  17. 18. <ul><li>Also called crowbar currents </li></ul><ul><li>Refers to direct path from V DD to V GND during switching events </li></ul>Short Circuit Currents scr is short circuit rise time And scf is short circuit fall time P SC is short circuit power consumption I SC is the short circuit current consumed Δ t sc is the duration for which the short circuit current flows I SC , avg is the average crowbar current during rise and fall.
  18. 19. C sc is short circuit capacitance
  19. 20. Short Circuit Currents - another approach <ul><li>Rise/Fall time of input wave is greater than 0, so short circuit current will flow </li></ul><ul><li>Let VTn=VTp=VT </li></ul><ul><li>Consider 0 to 1 transition. Initially when Vin was 0, pmos was on and nmos was off </li></ul><ul><li>As point 1 approaches nmos is turned on as Vin =VT. pmos is still on </li></ul><ul><li>Short circuit current flows from VDD to GND </li></ul><ul><li>Current increases to maximum when both devices enter saturation </li></ul><ul><li>As point 2 approaches, pmos shuts down, crowbar current stops flowing </li></ul>V T VDD-V T 1 2 time voltage
  20. 21. Direct Path currents contd. Area of an equilateral triangle is 1/2base. perpendicular P=VI, E=Pt
  21. 22. f 0 to1 or 1 to 0 is switching frequency ts is 0 to 100% transition time tr(f) is 10 to 90% transition time
  22. 23. How to minimize crowbar currents? <ul><li>Consider a CMOS inverter with a 0 to 1 transition at the input </li></ul><ul><li>Let C L be very large </li></ul><ul><li>Thus, output will make a a 1 to 0 transition t f =0.69R N C L </li></ul><ul><li>This delay will also be large </li></ul><ul><li>Assume that input rise time is very small </li></ul><ul><li>Input will change through transition before output changes </li></ul><ul><li>Vs of pmos is at VDD </li></ul><ul><li>VD of pmos will be approximately at VDD </li></ul><ul><li>Thus VDS of pmos is approx 0 </li></ul><ul><li>Device shuts off before delivering any current </li></ul>
  23. 24. How to minimize crowbar currents? <ul><li>Consider again a CMOS inverter with a 0 to 1 transition at the input </li></ul><ul><li>Let C L be very small </li></ul><ul><li>Thus, output will make a a 1 to 0 transition t f =0.69R N C L </li></ul><ul><li>This delay will also be small </li></ul><ul><li>Assume that input rise time is very large </li></ul><ul><li>Input will change through transition slowly </li></ul><ul><li>Vs of pmos is at VDD </li></ul><ul><li>VD of pmos will be approximately at 0 </li></ul><ul><li>Thus VDS of pmos is approx VDD </li></ul><ul><li>Maximum short circuit current is </li></ul><ul><li>delivered </li></ul>
  24. 25. Short Circuit Currents
  25. 26. How to keep Short-Circuit Currents Low? Short circuit current goes to zero if t fall >> t rise , but can’t do this for cascade logic, so ... Input slope is fixed
  26. 27. Conclusion… <ul><li>Large C L may mean less short circuit power, but it will also mean longer delays </li></ul><ul><li>Will lead to short circuit currents in fan out gate as their tin will be slow!! </li></ul><ul><li>Local Optimization pointless! </li></ul><ul><li>To minimize power consumption in a global way </li></ul><ul><li>Match rise/fall times of input and output waveforms </li></ul>
  27. 28. Minimizing Short-Circuit Power Vdd =1.5 Vdd =2.5 Vdd =3.3
  28. 29. <ul><li>Notice in the previous graph that when tsin/tsout=1 Power Dissipation is minimum </li></ul><ul><li>Reducing V DD leads to lower power consumption </li></ul><ul><li>Point 1 is VTn Point2 is VDD-VTP </li></ul><ul><li>If 2 lies before 1 short circuit power consumption is 0! </li></ul><ul><li>However circuit will be slower </li></ul>V T VDD-V T 1 2 time voltage
  29. 30. Dynamic Power -Glitches Glitches are caused by arrival time of two separate input signals. If a given input signal arrives first and causes the output to switch, later another input signal arrives and causes the output to switch back to original value. Undesired Power dissipation ! Glitches propagate thought the fanout gate and cause further unintended transitions
  30. 31. <ul><li>To reduce glitches, </li></ul><ul><li>Signals should be made to arrive at roughly the same time </li></ul><ul><li>Certain architectures and logics are made glitch free inherently </li></ul>
  31. 32. Static Power Consumption <ul><li>Caused by leakage currents due to </li></ul><ul><li>Reverse biased Source and drain junctions </li></ul><ul><li>Subthreshold currents and ie currents that flow when VGS is less than VT </li></ul>
  32. 33. Leakage Sub-threshold current one of most compelling issues in low-energy circuit design!
  33. 34. Reverse-Biased Diode Leakage JS = 10-100 pA/  m2 at 25 deg C for 0.25  m CMOS JS doubles for every 9 deg C!
  34. 35. Junction Leakage currents are caused by thermally generated carriers. Their value increases with increasing temperature. At 85 degrees Celsius, (upper bound for junction temperature) their value increases by 60 times over room temperature value.
  35. 36. Subthreshold Leakage Component
  36. 37. Sub threshold Leakage issues Closer V T is to 0 V, larger is the static power dissipation as I D becomes larger L is getting smaller as source and drain are getting closer Supply voltages are being scaled while keeping V T constant. This leads to increase in delay –see next slide. As Supply voltage goes down to 2V T,, performance goes down substantially. If V T is lowered, performance improves, sub threshold leakage becomes an issue i.e. Trade off between power and delay!
  37. 38. Delay as a function of V DD V T =0.5V
  38. 39. Static Power Consumption Wasted energy … Should be avoided in almost all cases, but could help reducing energy in others (e.g. sense amps)
  39. 40. Principles for Power Reduction <ul><li>Prime choice: Reduce voltage! </li></ul><ul><ul><li>Recent years have seen an acceleration in supply voltage reduction </li></ul></ul><ul><ul><li>Design at very low voltages still open question (0.6 … 0.9 V by 2010!) </li></ul></ul><ul><li>Reduce switching activity </li></ul><ul><li>Reduce physical capacitance </li></ul><ul><ul><li>Device Sizing: for F =20 </li></ul></ul><ul><ul><ul><li>f opt (energy)=3.53, f opt (performance)=4.47 </li></ul></ul></ul>
  40. 41. Modification for Circuits with Reduced Swing
  41. 42. Power Equation Static power loss in pseudo nmos only half the time!
  42. 43. POWER DELAY TRADE OFF We want low power and small delay. Why not minimize the product? P avg is average Power consumed t p is average delay Only dominant term in Power Equation Assume Gate switches at maximum possible rate so rise and fall
  43. 44. To Reduce PDP <ul><li>Reduce Load Capacitance </li></ul><ul><li>Reduce Supply Voltage </li></ul><ul><li>PDP does not capture the fact that reducing Supply Voltage lowers Power consumption, but increases delay </li></ul><ul><li>New metric Energy Delay Product is defined (EDP) </li></ul><ul><li>EDP=PDP  t p </li></ul>
  44. 45. Differentiating EDp w.r.t. V DD and putting the result equal to 0
  45. 46. V DD (V) V T =0.5V
  46. 47. LPVD Lecture-1   <ul><li>Three components : </li></ul><ul><li>Dynamic Capacitive (Switching) Power: </li></ul><ul><li>- Charging and Discharging the capacitance. </li></ul><ul><li>- Still dominant component in current technology. </li></ul><ul><li>Short-circuit Power: </li></ul><ul><li>- Due to current flow from Vdd to GND. </li></ul><ul><li>- Worst in case of slow transition. </li></ul><ul><li>Leakage Current: </li></ul><ul><li>- Diodes Leakage around transistor and N-well. </li></ul><ul><li>- Increases 20 times for each new technology. </li></ul><ul><li>- Becoming insignificant to the dominant factor . </li></ul>SOURCES OF POWER DISSIPATION
  47. 48. LPVD Lecture-1   <ul><li>Reduced switching voltage: </li></ul><ul><li>- P=CfV 2 Saving in power but performance is lost. </li></ul><ul><li>- Transistors become slow due to low V t , leakage </li></ul><ul><li>current increases. Noise margins problem increases. </li></ul><ul><li>Reduced leakage and Static Current: </li></ul><ul><li>- Can be reduce by transistor sizing, layout techniques, </li></ul><ul><li>and careful circuit design. </li></ul><ul><li>- Circuit models can be turned off if not in used. </li></ul><ul><li>Use Standby Mode : </li></ul><ul><li>- Clock disabling and power-off of selected logic </li></ul><ul><li>blocks. </li></ul><ul><li> </li></ul>LOW POWER APPROACHES
  48. 49. LPVD Lecture-1   <ul><li>Reduced Switching Capacitance: </li></ul><ul><li>- Can not reduce blindly. Reduce product of cap and </li></ul><ul><li>switching frequency. </li></ul><ul><li>- Signals with high switching frequency are routed with </li></ul><ul><li>minimum parasitic cap. </li></ul><ul><li>- Node with large Capacitance are not allowed to switch </li></ul><ul><li>at high frequency. </li></ul><ul><li>-capacitance reduction is achieved at different level. </li></ul><ul><li>Material, technology, physical design, circuit technique . </li></ul>
  49. 50. LPVD Lecture-1   <ul><li>Reduced switching Frequency: </li></ul><ul><li>- Eliminate logic switching that is not necessary for </li></ul><ul><li>computation to reduce the frequency. </li></ul><ul><li>- Change the logic family, use different coding method, </li></ul><ul><li>number representation system. They can alter the </li></ul><ul><li>switching frequency of the design </li></ul><ul><li>Adiabatic Computing : </li></ul><ul><ul><li>- Avoid gain / loss of heat during computing. </li></ul></ul>
  50. 51. Thank you ………….