Thesis F. Redaelli UIC Slides EN

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Thesis F. Redaelli UIC Slides EN

  1. 1. T ask S cheduling T ailored for P artially D ynamically R econfigurable D evices UIC Thesis Defence May 2007 .:: Francesco Redaelli ::.
  2. 2. Outline <ul><li>Outline </li></ul><ul><li>Context Definition </li></ul><ul><li>Problem Definition </li></ul><ul><li>Reconfiguration Features </li></ul><ul><li>State of the Art </li></ul><ul><li>ILP Formulation </li></ul><ul><li>Reconfiguration-aware Scheduler </li></ul><ul><li>Experimental Results </li></ul><ul><li>Conclusion and Future Works </li></ul>
  3. 3. Aims <ul><li>(A1) Definition of a formal model for the scheduling problem in a partially dynamically reconfigurable scenario </li></ul><ul><li>(A2) Development of a heuristic method to solve in reasonable time the proposed scheduling problem </li></ul><ul><li>(A3) Validation of the proposed ILP model and heuristic scheduler </li></ul>
  4. 4. What’s next… <ul><li>Outline </li></ul><ul><li>Context Definition </li></ul><ul><li>Problem Definition </li></ul><ul><li>Reconfiguration Features </li></ul><ul><li>State of the Art </li></ul><ul><li>ILP Formulation </li></ul><ul><li>Reconfiguration-aware Scheduler </li></ul><ul><li>Experimental Results </li></ul><ul><li>Conclusion and Future Works </li></ul>
  5. 5. Context Definition
  6. 6. Reconfiguration <ul><li>The process of physically altering the location or functionality of network or system elements. Automatic configuration describes the way sophisticated networks can readjust themselves in the event of a link or device failing, enabling the network to continue operation. </li></ul><ul><li>Gerald Estrin, 1960 </li></ul>
  7. 7. Reconfiguration Partial Total
  8. 8. Reconfiguration Partial Total Dynamic
  9. 9. Reconfiguration in everyday life <ul><li>Soccer </li></ul>Hockey Football (Partial – Static)‏ (Complete – Static)‏ (Partial – Dynamic)‏
  10. 10. What’s next… <ul><li>Outline </li></ul><ul><li>Context Definition </li></ul><ul><li>Problem Definition </li></ul><ul><li>Reconfiguration Features </li></ul><ul><li>State of the Art </li></ul><ul><li>ILP Formulation </li></ul><ul><li>Reconfiguration-aware Scheduler </li></ul><ul><li>Experimental Results </li></ul><ul><li>Conclusion and Future Works </li></ul>
  11. 11. Problem Definition 1 of 2 <ul><li>G=<O,P> </li></ul><ul><li>O set of tasks </li></ul><ul><li>P set of dependences between tasks (edges) </li></ul><ul><li>schedule the task graph onto a dynamically partially reconfigurable architecture with an area constraint Atot in order to minimize the completion time. </li></ul><ul><li>Each task i is characterized by: </li></ul><ul><ul><li>ty i the type of the task; </li></ul></ul><ul><ul><li>c i the area occupied onto the FPGA; </li></ul></ul><ul><ul><li>t r i the time needed to reconfigure the task onto the FPGA; </li></ul></ul><ul><ul><li>t e i the execution time of the task; </li></ul></ul>
  12. 12. Problem Definition 2 of 2 <ul><li>A solution for this problem is found giving for eack task: </li></ul><ul><ul><li>the reconfiguration beginning time; </li></ul></ul><ul><ul><li>the execution beginning time; </li></ul></ul><ul><ul><li>the position on the FPGA where it is mapped. </li></ul></ul><ul><li>The FPGA area constraint Atot is given as the number of columns available for the reconfigurable hardware. </li></ul><ul><li>The area property c i of each task is given as the number of adjacent columns onto the FPGA. </li></ul>
  13. 13. What’s next… <ul><li>Outline </li></ul><ul><li>Context Definition </li></ul><ul><li>Problem Definition </li></ul><ul><li>Reconfiguration Features </li></ul><ul><li>State of the Art </li></ul><ul><li>ILP Formulation </li></ul><ul><li>Reconfiguration-aware Scheduler </li></ul><ul><li>Experimental Results </li></ul><ul><li>Conclusion and Future Works </li></ul>
  14. 14. Reconfiguration Features <ul><li>Partially Dynamically Reconfigurable FPGAs allow: </li></ul><ul><li>Configuration prefetching </li></ul><ul><li>Module reuse </li></ul><ul><li>Anti-fragmentation techniques </li></ul><ul><li>Try to exploit these features in the best way to schedule the task graph </li></ul>
  15. 15. Configuration Prefetching Ti: execution of task i Ri: configuration of task i
  16. 16. Module Reuse Ti: execution of task i Ri: configuration of task i
  17. 17. Anti-Fragmentation Techniques Ti: execution of task i Ri: configuration of task i
  18. 18. What’s next… <ul><li>Outline </li></ul><ul><li>Context Definition </li></ul><ul><li>Problem Definition </li></ul><ul><li>Reconfiguration Features </li></ul><ul><li>State of the Art </li></ul><ul><li>ILP Formulation </li></ul><ul><li>Reconfiguration-aware Scheduler </li></ul><ul><li>Experimental Results </li></ul><ul><li>Conclusion and Future Works </li></ul>
  19. 19. State Of the Art 1 of 3 <ul><li>Scheduling done using a list-based approach </li></ul><ul><li>HW/SW Co-design usually considered </li></ul><ul><li>Anti-fragmentation techniques are not considered: </li></ul><ul><ul><li>First Fit </li></ul></ul><ul><ul><li>Best Fit </li></ul></ul><ul><li>Most frequently used deconfiguration policy is the LIU one with no limitation </li></ul>
  20. 20. State Of the Art 2 of 3 <ul><li>[BBD06a] S. Banerjee, E. Bozorgzadeh, N. D. Dutt “ Integrating physical constraints in HW-SW Partitioning for Architectures with partial dynamic reconfiguration ”, IEEE Transactions on very large scale integration system, vol. 14, no. 11, november 2006 </li></ul><ul><li>PRO: </li></ul><ul><li>Extendible for only HW environments; </li></ul><ul><li>Configuration prefetching; </li></ul><ul><li>Explicit adjacent column based constraints for task mapping; </li></ul><ul><li>Partial reconfiguration; </li></ul><ul><li>CONS: </li></ul><ul><li>No module reuse; </li></ul>
  21. 21. State Of the Art 3 of 3 <ul><li>[BBD06b] S. Banerjee, E. Bozorgzadeh, N. Dutt, ” PARLGRAN: parallelism granularity selection for scheduling task chains on dynamically reconfigurable architectures ”, In Proceedings of Asia and South Pacific Design Automation Conference, ASP-DAC, 24-27 January, 2006. </li></ul><ul><li>PRO: </li></ul><ul><li>Thought for only HW environments; </li></ul><ul><li>Configuration prefetching; </li></ul><ul><li>Anti-fragmentation techniques for linear task graphs; </li></ul><ul><li>Partial reconfiguration; </li></ul><ul><li>CONS: </li></ul><ul><li>Only linear task graphs; </li></ul><ul><li>No module reuse. </li></ul>
  22. 22. What’s next… <ul><li>Outline </li></ul><ul><li>Context Definition </li></ul><ul><li>Problem Definition </li></ul><ul><li>Reconfiguration Features </li></ul><ul><li>State of the Art </li></ul><ul><li>ILP Formulation </li></ul><ul><li>Reconfiguration-aware Scheduler </li></ul><ul><li>Experimental Results </li></ul><ul><li>Conclusion and Future Works </li></ul>
  23. 23. ILP Formulation - Basic Idea
  24. 24. ILP Formulation 1 of 2 <ul><li>Constants: </li></ul><ul><ul><li>ty ij equal to 1 if task i has the same type of task j; </li></ul></ul><ul><ul><li>t r i the time needed to reconfigure the task onto the FPGA; </li></ul></ul><ul><ul><li>t e i the execution time of the task; </li></ul></ul><ul><ul><li>c i the number of adjacent columns occupied onto the FPGA. </li></ul></ul><ul><li>Variables: </li></ul><ul><ul><li>r itk = 1 if task i is on the FPGA at time t starting from column k </li></ul></ul><ul><ul><li>= 0 otherwise </li></ul></ul><ul><ul><li>mr i = 1 if task i exploits module reuse </li></ul></ul><ul><ul><li>= 0 otherwise </li></ul></ul><ul><ul><li>rec it = 1 if task i is reconfigured at time t </li></ul></ul><ul><ul><li>= 0 otherwise </li></ul></ul>
  25. 25. ILP Formulation 2 of 2 OBJECTIVE FUNCTION <ul><li>Variables (Cont'd)‏ </li></ul><ul><li>Son i : time when task i arrives on the FPGA </li></ul><ul><li>Soff i : time when task i is removed from the FPGA </li></ul><ul><li>Tf: task graph completion time </li></ul>
  26. 26. ILP Formulation – Constraints 1 of 5 1) Area constraint 2) Non overlap constraint 3) Right space
  27. 27. ILP Formulation – Constraints 2 of 5 4) Zero time 7) Always same column 8) Definition of on board time and offboard time
  28. 28. ILP Formulation – Constraints 3 of 5 9) Continuous usage 10) Reconfigured tasks constraints
  29. 29. ILP Formulation – Constraints 4 of 5 12) Permission of reuse 11) Single reconfiguration device 13) Reused task constraints
  30. 30. ILP Formulation – Constraints 5 of 5 14) Precedences 16) Final time constraint 15) Final time definition
  31. 31. What’s next… <ul><li>Outline </li></ul><ul><li>Context Definition </li></ul><ul><li>Problem Definition </li></ul><ul><li>Reconfiguration Features </li></ul><ul><li>State of the Art </li></ul><ul><li>ILP Formulation </li></ul><ul><li>Reconfiguration-aware Scheduler </li></ul><ul><li>Experimental Results </li></ul><ul><li>Conclusion and Future Works </li></ul>
  32. 32. Napoleon Reconfiguration-Aware Scheduler 1 of 3 <ul><li>Napoleon: heuristic reconfiguration-aware scheduler, list-based with priority function the ALAP value of a node. It allows out of order scheduling for particular task graphs. </li></ul><ul><li>It tries to exploits at best </li></ul><ul><ul><li>Configuration prefetching </li></ul></ul><ul><ul><li>Module reuse </li></ul></ul><ul><li>It also uses anti-fragmentation techniques to improve the quality of the solution </li></ul><ul><li>It tries to build a solution taking into account the constraints found in the ILP formulation of the problem </li></ul>
  33. 33. Napoleon Reconfiguration-Aware Scheduler 2 of 3 <ul><li>Anti-Fraqmentation Techniques: </li></ul><ul><ul><li>farthest placement </li></ul></ul>Ti: execution of task i Ri: configuration of task i
  34. 34. <ul><ul><li>limited deconfiguration </li></ul></ul>Ti: execution of task i Ri: configuration of task i Napoleon Reconfiguration-Aware Scheduler 3 of 3
  35. 35. What’s next… <ul><li>Outline </li></ul><ul><li>Context Definition </li></ul><ul><li>Problem Definition </li></ul><ul><li>Reconfiguration Features </li></ul><ul><li>State of the Art </li></ul><ul><li>ILP Formulation </li></ul><ul><li>Reconfiguration-aware Scheduler </li></ul><ul><li>Experimental Results </li></ul><ul><li>Conclusion and Future Works </li></ul>
  36. 36. Experimental Results <ul><li>GLPK [http://gnuwin32.sourceforge.net/packages/glpk.htm] has been used to solve the ILP instances </li></ul><ul><li>Benchmark </li></ul><ul><ul><li>Ten task graphs with ten nodes [BBD06a] </li></ul></ul><ul><ul><li>9135 task graphs with a number of nodes in a 10-1000 range </li></ul></ul>
  37. 37. Other Algorithms <ul><li>ASAP </li></ul><ul><li>ALAP </li></ul><ul><li>DyASAP </li></ul>These algorithms have been used to verify the real effectiveness of Napoleon They have been chosen as the most representative for the solution of our problem in the literature When a deconfiguration policy is used it is unlimited All these algorithms have been implemented <ul><li>ASAPS </li></ul><ul><li>ALAPS </li></ul><ul><li>DyASAPS </li></ul><ul><li>ASAPB </li></ul><ul><li>ALAPB </li></ul><ul><li>DyASAPB </li></ul><ul><li>ASAPLIU </li></ul><ul><li>ALAPLIU </li></ul><ul><li>DyASAPLIU </li></ul>
  38. 38. Results 1 of 4
  39. 39. Results 2 of 4
  40. 40. Results 3 of 4
  41. 41. Results 4 of 4
  42. 42. What’s next… <ul><li>Outline </li></ul><ul><li>Context Definition </li></ul><ul><li>Problem Definition </li></ul><ul><li>Reconfiguration Features </li></ul><ul><li>State of the Art </li></ul><ul><li>ILP Formulation </li></ul><ul><li>Reconfiguration-aware Scheduler </li></ul><ul><li>Experimental Results </li></ul><ul><li>Conclusion and Future Works </li></ul>
  43. 43. Conclusions and Future Works <ul><li>Conclusions: </li></ul><ul><ul><li>ILP model formulation for the scheduling problem in a partially dynamically reconfigurable scenario --> (A1) </li></ul></ul><ul><ul><li>Napoleon heuristic method based on the ILP formulation --> (A2) </li></ul></ul><ul><ul><li>Napoleon obtains schedule length (in average) 18.6% better than the other algorithms --> (A3) </li></ul></ul><ul><li>Future works </li></ul><ul><ul><li>Integrate Napoleon into a general framework, to create a scheduling/reconfiguration-aware partitioning </li></ul></ul><ul><ul><li>Integrate Napoleon in DRESD-HLR to complete the design flow to implement large applications onto partially dynamically reconfigurable devices </li></ul></ul><ul><ul><li>Try new anti-fragmentation techniques </li></ul></ul>
  44. 44. Questions? Thank you…

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