H igh  P erformance   P rocessors   and  S ystems   PdM – UIC joint master 2007 Instructor: Prof. Donatella Sciuto HPPS @ ...
Outline <ul><li>DReAMS </li></ul><ul><ul><li>Matteo Murgida </li></ul></ul><ul><ul><li>Alessandro Panella </li></ul></ul><...
What’s next <ul><li>DReAMS </li></ul><ul><ul><li>Matteo Murgida </li></ul></ul><ul><ul><li>Alessandro Panella </li></ul></...
D ynamic  Re configurability  A pplied   to  M ulti-FPGA  S ystems
DReAMS <ul><li>Dynamic Reconfigurability </li></ul><ul><li>Applied to Multi-FPGA Systems </li></ul><ul><ul><li>Branch of D...
Multi-FPGA Theoretical and  Simulation Model  1/2 <ul><li>Project’s goals: </li></ul><ul><ul><li>Produce a multi-FPGA theo...
Multi-FPGA Theoretical and Simulation Model  2/2 <ul><li>Project scheduling </li></ul><ul><ul><li>Detect relevant paramete...
Architecture Definition   1/3 <ul><li>Three Layers: </li></ul><ul><ul><li>Overall Multi-FPGA System </li></ul></ul><ul><ul...
Architecture Definition  2/3
Architecture Definition   3/3 <ul><li>Project Schedule </li></ul><ul><ul><li>Study how to use Digilent Spartan-3 boards </...
What’s next <ul><li>DReAMS </li></ul><ul><ul><li>Matteo Murgida </li></ul></ul><ul><ul><li>Alessandro Panella </li></ul></...
RE configurable  C ommunication  I nfrastructure  F or   E mbedded-systems
Project's objectives <ul><li>Communication infrastructure exploration </li></ul><ul><ul><li>Technologies and paradigms </l...
Schedule – Project Organization <ul><li>Literature analysis </li></ul><ul><ul><li>Reconfigurable devices and systems  </li...
What’s next <ul><li>DReAMS </li></ul><ul><ul><li>Matteo Murgida </li></ul></ul><ul><ul><li>Alessandro Panella </li></ul></...
R econfiguration  O riented  Me trics
Motivations and Goals <ul><li>Rationale </li></ul><ul><ul><li>Requirements-driven Reconfigurable SoC Communication Infrast...
Schedule - Project Organization <ul><li>Study and analysis of well-known metrics </li></ul><ul><ul><li>TCP/IP Protocols </...
What’s next <ul><li>DReAMS </li></ul><ul><ul><li>Matteo Murgida </li></ul></ul><ul><ul><li>Alessandro Panella </li></ul></...
P rocessing  E lements  RE configuration  I n   R econfigurable  A rchitectures
Project Environment <ul><li>Multi Processing Elements SoC Architecture </li></ul><ul><ul><li>Support Dynamic Partial Recon...
Goals <ul><li>Implement and test a single Processing Element </li></ul><ul><ul><li>Based on Harvard Architecture </li></ul...
Schedule - Project Organization <ul><li>Bitstream’s structure analysis </li></ul><ul><ul><li>Check differences between tot...
What’s next <ul><li>DReAMS </li></ul><ul><ul><li>Matteo Murgida </li></ul></ul><ul><ul><li>Alessandro Panella </li></ul></...
Development of an OS architecture-independent layer for dynamic reconfiguration
Scenario and Goals <ul><li>Current scenario </li></ul><ul><ul><li>Operating system support for dynamic reconfigurable arch...
Schedule – Project Organization <ul><li>Feasibility study </li></ul><ul><ul><li>Study of the existing operating systems de...
What’s next <ul><li>DReAMS </li></ul><ul><ul><li>Matteo Murgida </li></ul></ul><ul><ul><li>Alessandro Panella </li></ul></...
Effects of 2D Reconfiguration in a Reconfigurable System
Effects of 2D Reconfiguration <ul><li>New Generation of FPGAs </li></ul><ul><ul><li>Virtex-4 and Virtex-5 </li></ul></ul><...
Project Goals <ul><li>Project goals: </li></ul><ul><ul><li>Analyse effects of the new approach </li></ul></ul><ul><ul><li>...
Schedule – Project Organization <ul><li>First Phase: </li></ul><ul><ul><li>General analysis of 2D reconfiguration </li></u...
What’s next <ul><li>DReAMS </li></ul><ul><ul><li>Matteo Murgida </li></ul></ul><ul><ul><li>Alessandro Panella </li></ul></...
Relocation for 2D Reconfigurable Systems
2D Relocation <ul><li>Self dynamical run-time 2D reconfiguration </li></ul><ul><ul><li>Virtex-4 and Virtex-5 </li></ul></u...
Schedule – Project Organization <ul><li>First Phase: </li></ul><ul><ul><li>Examine Xilinx documentation on Virtex-4 and 5 ...
What’s next <ul><li>DReAMS </li></ul><ul><ul><li>Matteo Murgida </li></ul></ul><ul><ul><li>Alessandro Panella </li></ul></...
H igh  L evel  R econfiguration
Goals <ul><li>General  </li></ul><ul><ul><li>Join isomorphic reconfigurable partitioning theory with reconfigurable schedu...
Salomone++ workflow <ul><li>From specification to optimized scheduling… </li></ul>Specification Tree Structure Graph Analy...
Schedule optimization <ul><li>Evaluates a scheduling for a target architecture…  </li></ul><ul><li>Based on simply conside...
Project organization <ul><li>First phase:  </li></ul><ul><ul><li>Development of the workflow  </li></ul></ul><ul><ul><ul><...
Questions
Upcoming SlideShare
Loading in …5
×

HPPS 2007 Projects Presentation

915 views

Published on

HPPS 2007 Projects Presentation

Published in: Technology, Design
0 Comments
0 Likes
Statistics
Notes
  • Be the first to comment

  • Be the first to like this

No Downloads
Views
Total views
915
On SlideShare
0
From Embeds
0
Number of Embeds
43
Actions
Shares
0
Downloads
30
Comments
0
Likes
0
Embeds 0
No embeds

No notes for slide
  • HPPS 2007 Projects Presentation

    1. 1. H igh P erformance P rocessors and S ystems PdM – UIC joint master 2007 Instructor: Prof. Donatella Sciuto HPPS @ PdM – March 2007
    2. 2. Outline <ul><li>DReAMS </li></ul><ul><ul><li>Matteo Murgida </li></ul></ul><ul><ul><li>Alessandro Panella </li></ul></ul><ul><li>CITiES </li></ul><ul><ul><li>Simone Corbetta </li></ul></ul><ul><ul><li>Alessandro Meroni </li></ul></ul><ul><ul><li>Alessio Montone </li></ul></ul><ul><li>Operating System </li></ul><ul><ul><li>Ivan Beretta </li></ul></ul><ul><li>Polaris </li></ul><ul><ul><li>Massimo Morandi </li></ul></ul><ul><ul><li>Marco Novati </li></ul></ul><ul><li>HLR </li></ul><ul><ul><li>Marco Maggioni </li></ul></ul>
    3. 3. What’s next <ul><li>DReAMS </li></ul><ul><ul><li>Matteo Murgida </li></ul></ul><ul><ul><li>Alessandro Panella </li></ul></ul><ul><li>CITiES </li></ul><ul><ul><li>Simone Corbetta </li></ul></ul><ul><ul><li>Alessandro Meroni </li></ul></ul><ul><ul><li>Alessio Montone </li></ul></ul><ul><li>Operating System </li></ul><ul><ul><li>Ivan Beretta </li></ul></ul><ul><li>Polaris </li></ul><ul><ul><li>Massimo Morandi </li></ul></ul><ul><ul><li>Marco Novati </li></ul></ul><ul><li>HLR </li></ul><ul><ul><li>Marco Maggioni </li></ul></ul>
    4. 4. D ynamic Re configurability A pplied to M ulti-FPGA S ystems
    5. 5. DReAMS <ul><li>Dynamic Reconfigurability </li></ul><ul><li>Applied to Multi-FPGA Systems </li></ul><ul><ul><li>Branch of DRESD project </li></ul></ul><ul><ul><li>Inherits architectures and tools </li></ul></ul><ul><li>Automatic workflow from VHDL system description to FPGA implementation </li></ul><ul><ul><li>VHDL parsing and system simulation </li></ul></ul><ul><ul><li>System creation over a specific architecture </li></ul></ul><ul><ul><li>Bitstream creation and download onto FPGAs </li></ul></ul>
    6. 6. Multi-FPGA Theoretical and Simulation Model 1/2 <ul><li>Project’s goals: </li></ul><ul><ul><li>Produce a multi-FPGA theoretical model </li></ul></ul><ul><ul><ul><li>Architecture-independent </li></ul></ul></ul><ul><ul><ul><li>Must capture all relevant features </li></ul></ul></ul><ul><ul><li>Model Validation using several benchmarks </li></ul></ul><ul><ul><ul><li>Definition/Identification of the set of benchmarks </li></ul></ul></ul><ul><ul><ul><li>DO </li></ul></ul></ul><ul><ul><ul><ul><li>VHDL description analysis </li></ul></ul></ul></ul><ul><ul><ul><ul><li>Partitioning </li></ul></ul></ul></ul><ul><ul><ul><ul><li>Writing a SystemC/VHDL model </li></ul></ul></ul></ul><ul><ul><ul><ul><li>Simulation </li></ul></ul></ul></ul><ul><ul><ul><li>WHILE(No more improvement) </li></ul></ul></ul>
    7. 7. Multi-FPGA Theoretical and Simulation Model 2/2 <ul><li>Project scheduling </li></ul><ul><ul><li>Detect relevant parameters of Multi-FPGA systems </li></ul></ul><ul><ul><li>Analyze objective (cost) functions and architecture constraints </li></ul></ul><ul><ul><ul><li>Dimension </li></ul></ul></ul><ul><ul><ul><li>Connections bandwidth </li></ul></ul></ul><ul><ul><ul><li>Power consumption </li></ul></ul></ul><ul><ul><ul><li>… </li></ul></ul></ul><ul><ul><li>Create a valid theoretical model </li></ul></ul><ul><ul><li>Benchmarks identification/definition </li></ul></ul><ul><ul><li>Iterating process (analysis + partitioning + simulation) </li></ul></ul><ul><ul><li>System implementation on Spartan-3 Multi-FPGA architecture </li></ul></ul>
    8. 8. Architecture Definition 1/3 <ul><li>Three Layers: </li></ul><ul><ul><li>Overall Multi-FPGA System </li></ul></ul><ul><ul><ul><li>Net Topology Definition: mesh, ring, … </li></ul></ul></ul><ul><ul><li>Single FPGA </li></ul></ul><ul><ul><ul><li>Division between fix and reconfigurable parts </li></ul></ul></ul><ul><ul><ul><li>IP-Core selection </li></ul></ul></ul><ul><ul><ul><li>Internal Communication Infrastructure </li></ul></ul></ul><ul><ul><li>Communication Infrastructure </li></ul></ul><ul><ul><ul><li>Physical connections among FPGAs </li></ul></ul></ul><ul><ul><ul><li>Communication protocol </li></ul></ul></ul><ul><li>Development Environment: Digilent Spartan-3 boards </li></ul><ul><li>Final goal: distribuited dynamic reconfigurability </li></ul>
    9. 9. Architecture Definition 2/3
    10. 10. Architecture Definition 3/3 <ul><li>Project Schedule </li></ul><ul><ul><li>Study how to use Digilent Spartan-3 boards </li></ul></ul><ul><ul><li>Study its external interfaces and find a way to connect two or more boards together </li></ul></ul><ul><ul><li>Design the architecture of a single FPGA including the correct communication infrastructure </li></ul></ul><ul><ul><li>Develop the communication protocol </li></ul></ul><ul><ul><li>Connect two boards together </li></ul></ul><ul><ul><li>Develop a simple distribuited application to test the validity of the proposed approach </li></ul></ul>
    11. 11. What’s next <ul><li>DReAMS </li></ul><ul><ul><li>Matteo Murgida </li></ul></ul><ul><ul><li>Alessandro Panella </li></ul></ul><ul><li>CITiES </li></ul><ul><ul><li>Simone Corbetta </li></ul></ul><ul><ul><li>Alessandro Meroni </li></ul></ul><ul><ul><li>Alessio Montone </li></ul></ul><ul><li>Operating System </li></ul><ul><ul><li>Ivan Beretta </li></ul></ul><ul><li>Polaris </li></ul><ul><ul><li>Massimo Morandi </li></ul></ul><ul><ul><li>Marco Novati </li></ul></ul><ul><li>HLR </li></ul><ul><ul><li>Marco Maggioni </li></ul></ul>
    12. 12. RE configurable C ommunication I nfrastructure F or E mbedded-systems
    13. 13. Project's objectives <ul><li>Communication infrastructure exploration </li></ul><ul><ul><li>Technologies and paradigms </li></ul></ul><ul><ul><li>State of the art </li></ul></ul><ul><ul><ul><li>Advantages and pitfalls </li></ul></ul></ul><ul><ul><ul><li>Comparison </li></ul></ul></ul><ul><li>Communication infrastructure for reconfigurable systems </li></ul><ul><ul><li>CI requirements tailored for reconfigurable systems </li></ul></ul>
    14. 14. Schedule – Project Organization <ul><li>Literature analysis </li></ul><ul><ul><li>Reconfigurable devices and systems </li></ul></ul><ul><ul><ul><li>Contextualization </li></ul></ul></ul><ul><ul><ul><li>Communication needs </li></ul></ul></ul><ul><ul><li>Communication infrastructure state of the art </li></ul></ul><ul><ul><ul><li>Paradigms </li></ul></ul></ul><ul><ul><ul><ul><li>analysis </li></ul></ul></ul></ul><ul><ul><ul><ul><li>(potential) improvements </li></ul></ul></ul></ul><ul><ul><li>Communication infrastructure for reconfigurable systems </li></ul></ul><ul><li>Implementation </li></ul><ul><ul><li>Subject to the De Micheli VHDL description </li></ul></ul>
    15. 15. What’s next <ul><li>DReAMS </li></ul><ul><ul><li>Matteo Murgida </li></ul></ul><ul><ul><li>Alessandro Panella </li></ul></ul><ul><li>CITiES </li></ul><ul><ul><li>Simone Corbetta </li></ul></ul><ul><ul><li>Alessandro Meroni </li></ul></ul><ul><ul><li>Alessio Montone </li></ul></ul><ul><li>Operating System </li></ul><ul><ul><li>Ivan Beretta </li></ul></ul><ul><li>Polaris </li></ul><ul><ul><li>Massimo Morandi </li></ul></ul><ul><ul><li>Marco Novati </li></ul></ul><ul><li>HLR </li></ul><ul><ul><li>Marco Maggioni </li></ul></ul>
    16. 16. R econfiguration O riented Me trics
    17. 17. Motivations and Goals <ul><li>Rationale </li></ul><ul><ul><li>Requirements-driven Reconfigurable SoC Communication Infrastructure design </li></ul></ul><ul><ul><ul><li>e.g. QoS w.r.t. Load Balancing </li></ul></ul></ul><ul><li>Objectives </li></ul><ul><ul><li>Definition and Validation of a set of Metrics tailored to identification and definition of the more effective Communication Infrastructure for Multi Processing Elements SoC architecture </li></ul></ul><ul><ul><li>Validation framework definition </li></ul></ul><ul><ul><ul><li>Simulator implementation </li></ul></ul></ul>
    18. 18. Schedule - Project Organization <ul><li>Study and analysis of well-known metrics </li></ul><ul><ul><li>TCP/IP Protocols </li></ul></ul><ul><ul><li>Systems migration between different Tier </li></ul></ul><ul><li>Evaluation of different configurations of communication infrastructures </li></ul><ul><ul><li>Topology (bus, point-to-point, cross-bar, NoC, …) </li></ul></ul><ul><ul><li>Communication (connection-less, package-switching, circuit-switching, …) </li></ul></ul><ul><li>Definition of metrics considering: </li></ul><ul><ul><li>Reconfigurable System </li></ul></ul><ul><ul><li>Dynamic changing of communication infrastructure elements </li></ul></ul><ul><ul><li>Quality of Service </li></ul></ul><ul><li>Definition of a light framework </li></ul><ul><ul><li>Metrics Validation </li></ul></ul>
    19. 19. What’s next <ul><li>DReAMS </li></ul><ul><ul><li>Matteo Murgida </li></ul></ul><ul><ul><li>Alessandro Panella </li></ul></ul><ul><li>CITiES </li></ul><ul><ul><li>Simone Corbetta </li></ul></ul><ul><ul><li>Alessandro Meroni </li></ul></ul><ul><ul><li>Alessio Montone </li></ul></ul><ul><li>Operating System </li></ul><ul><ul><li>Ivan Beretta </li></ul></ul><ul><li>Polaris </li></ul><ul><ul><li>Massimo Morandi </li></ul></ul><ul><ul><li>Marco Novati </li></ul></ul><ul><li>HLR </li></ul><ul><ul><li>Marco Maggioni </li></ul></ul>
    20. 20. P rocessing E lements RE configuration I n R econfigurable A rchitectures
    21. 21. Project Environment <ul><li>Multi Processing Elements SoC Architecture </li></ul><ul><ul><li>Support Dynamic Partial Reconfigurability </li></ul></ul><ul><ul><li>Deployable on FPGAs </li></ul></ul>
    22. 22. Goals <ul><li>Implement and test a single Processing Element </li></ul><ul><ul><li>Based on Harvard Architecture </li></ul></ul><ul><ul><li>Softcore Processor: MicroBlaze </li></ul></ul><ul><ul><li>It can be dynamically reconfigured on the device </li></ul></ul><ul><li>Main Problems </li></ul><ul><ul><li>On chip memory (BRAM) inizialization: current softwares (provided by FPGA’s vendors) support only total configuration bitstreams </li></ul></ul>
    23. 23. Schedule - Project Organization <ul><li>Bitstream’s structure analysis </li></ul><ul><ul><li>Check differences between total configuration bitstreams and partial bitstreams </li></ul></ul><ul><ul><li>Find position of embedded memory information within the bitstream </li></ul></ul><ul><li>Write bitstream memory initializator </li></ul><ul><li>Perform tests on physical devices </li></ul>
    24. 24. What’s next <ul><li>DReAMS </li></ul><ul><ul><li>Matteo Murgida </li></ul></ul><ul><ul><li>Alessandro Panella </li></ul></ul><ul><li>CITiES </li></ul><ul><ul><li>Simone Corbetta </li></ul></ul><ul><ul><li>Alessandro Meroni </li></ul></ul><ul><ul><li>Alessio Montone </li></ul></ul><ul><li>Operating System </li></ul><ul><ul><li>Ivan Beretta </li></ul></ul><ul><li>Polaris </li></ul><ul><ul><li>Massimo Morandi </li></ul></ul><ul><ul><li>Marco Novati </li></ul></ul><ul><li>HLR </li></ul><ul><ul><li>Marco Maggioni </li></ul></ul>
    25. 25. Development of an OS architecture-independent layer for dynamic reconfiguration
    26. 26. Scenario and Goals <ul><li>Current scenario </li></ul><ul><ul><li>Operating system support for dynamic reconfigurable architectures: </li></ul></ul><ul><ul><ul><li>Architecture specific (e.g. Caronte ) </li></ul></ul></ul><ul><ul><ul><li>Processor specific (e.g. PowerPC ) </li></ul></ul></ul><ul><ul><ul><li>Tied to a particular distribution (e.g. MontaVista Linux) </li></ul></ul></ul><ul><li>Project objective </li></ul><ul><ul><li>Definition of a new intermediate layer for an operating system which is: </li></ul></ul><ul><ul><ul><li>Able to support dynamic reconfiguration </li></ul></ul></ul><ul><ul><ul><li>Architecture independent </li></ul></ul></ul><ul><ul><ul><li>High-level Linux distro independent </li></ul></ul></ul><ul><ul><li>Implementation and validation using different FPGAs </li></ul></ul>
    27. 27. Schedule – Project Organization <ul><li>Feasibility study </li></ul><ul><ul><li>Study of the existing operating systems developed on the dynamic reconfigurable architectures defined in the DRESD Project </li></ul></ul><ul><li>Definition of the new layer </li></ul><ul><li>Application </li></ul><ul><ul><li>Integration of the new layer in an existing framework </li></ul></ul><ul><ul><li>Integration of the new layer in a different distribution executed on a different architecture </li></ul></ul><ul><ul><li>Implementation using Xilinx FPGAs: vp7, vp20 and vp30 </li></ul></ul>
    28. 28. What’s next <ul><li>DReAMS </li></ul><ul><ul><li>Matteo Murgida </li></ul></ul><ul><ul><li>Alessandro Panella </li></ul></ul><ul><li>CITiES </li></ul><ul><ul><li>Simone Corbetta </li></ul></ul><ul><ul><li>Alessandro Meroni </li></ul></ul><ul><ul><li>Alessio Montone </li></ul></ul><ul><li>Operating System </li></ul><ul><ul><li>Ivan Beretta </li></ul></ul><ul><li>Polaris </li></ul><ul><ul><li>Massimo Morandi </li></ul></ul><ul><ul><li>Marco Novati </li></ul></ul><ul><li>HLR </li></ul><ul><ul><li>Marco Maggioni </li></ul></ul>
    29. 29. Effects of 2D Reconfiguration in a Reconfigurable System
    30. 30. Effects of 2D Reconfiguration <ul><li>New Generation of FPGAs </li></ul><ul><ul><li>Virtex-4 and Virtex-5 </li></ul></ul><ul><ul><li>Allow bi-dimensional reconfiguration </li></ul></ul><ul><li>Improvements: </li></ul><ul><ul><li>Possibility for area and performance optimizations </li></ul></ul><ul><li>Increased complexity : </li></ul><ul><ul><li>In fragmentation management </li></ul></ul><ul><ul><li>In Placement </li></ul></ul><ul><ul><li>In Communication infrastructure creation </li></ul></ul><ul><ul><li>In the Bitstream generation phase </li></ul></ul>
    31. 31. Project Goals <ul><li>Project goals: </li></ul><ul><ul><li>Analyse effects of the new approach </li></ul></ul><ul><ul><li>Examine possible remedies to the new problems </li></ul></ul><ul><ul><li>Evaluate those solutions in various scenario </li></ul></ul>
    32. 32. Schedule – Project Organization <ul><li>First Phase: </li></ul><ul><ul><li>General analysis of 2D reconfiguration </li></ul></ul><ul><li>Second Phase: </li></ul><ul><ul><li>Detailed description of the new problems </li></ul></ul><ul><li>Third Phase: </li></ul><ul><ul><li>Analysis of possible solutions to those problems </li></ul></ul><ul><li>Fourth Phase: </li></ul><ul><ul><li>Evaluation of examined alternatives </li></ul></ul>
    33. 33. What’s next <ul><li>DReAMS </li></ul><ul><ul><li>Matteo Murgida </li></ul></ul><ul><ul><li>Alessandro Panella </li></ul></ul><ul><li>CITiES </li></ul><ul><ul><li>Simone Corbetta </li></ul></ul><ul><ul><li>Alessandro Meroni </li></ul></ul><ul><ul><li>Alessio Montone </li></ul></ul><ul><li>Operating System </li></ul><ul><ul><li>Ivan Beretta </li></ul></ul><ul><li>Polaris </li></ul><ul><ul><li>Massimo Morandi </li></ul></ul><ul><ul><li>Marco Novati </li></ul></ul><ul><li>HLR </li></ul><ul><ul><li>Marco Maggioni </li></ul></ul>
    34. 34. Relocation for 2D Reconfigurable Systems
    35. 35. 2D Relocation <ul><li>Self dynamical run-time 2D reconfiguration </li></ul><ul><ul><li>Virtex-4 and Virtex-5 </li></ul></ul><ul><ul><li>Relocation </li></ul></ul><ul><ul><ul><li>HW/SW solutions: advantages and disadvantages </li></ul></ul></ul><ul><ul><ul><li>BiRF </li></ul></ul></ul><ul><li>Project goals: </li></ul><ul><ul><li>Study of the new FPGA families </li></ul></ul><ul><ul><li>Analysis of the new bitstream structure </li></ul></ul><ul><ul><li>New version of BiRF ( BiRF 2 ) </li></ul></ul>
    36. 36. Schedule – Project Organization <ul><li>First Phase: </li></ul><ul><ul><li>Examine Xilinx documentation on Virtex-4 and 5 </li></ul></ul><ul><li>Second Phase: </li></ul><ul><ul><li>Generate Virtex-4 bitstreams to examine their structure </li></ul></ul><ul><li>Third Phase: </li></ul><ul><ul><li>Implement the new version of BiRF </li></ul></ul><ul><li>Fourth Phase: </li></ul><ul><ul><li>Validation of the results </li></ul></ul>
    37. 37. What’s next <ul><li>DReAMS </li></ul><ul><ul><li>Matteo Murgida </li></ul></ul><ul><ul><li>Alessandro Panella </li></ul></ul><ul><li>CITiES </li></ul><ul><ul><li>Simone Corbetta </li></ul></ul><ul><ul><li>Alessandro Meroni </li></ul></ul><ul><ul><li>Alessio Montone </li></ul></ul><ul><li>Operating System </li></ul><ul><ul><li>Ivan Beretta </li></ul></ul><ul><li>Polaris </li></ul><ul><ul><li>Massimo Morandi </li></ul></ul><ul><ul><li>Marco Novati </li></ul></ul><ul><li>HLR </li></ul><ul><ul><li>Marco Maggioni </li></ul></ul>
    38. 38. H igh L evel R econfiguration
    39. 39. Goals <ul><li>General </li></ul><ul><ul><li>Join isomorphic reconfigurable partitioning theory with reconfigurable scheduling performed by Salomone and area occupancy metric </li></ul></ul><ul><ul><li>Evaluate quality of the given schedule result and optimize architecture exploiting </li></ul></ul><ul><ul><li>Provide a common interface to represent TDG and scheduling output </li></ul></ul><ul><li>Specific </li></ul><ul><ul><li>Automatize benchmarks production </li></ul></ul><ul><ul><li>Re-implementing Salomone to adopt the new defined interface </li></ul></ul><ul><ul><li>Provide a graphical representation for the schedules </li></ul></ul>
    40. 40. Salomone++ workflow <ul><li>From specification to optimized scheduling… </li></ul>Specification Tree Structure Graph Analysis Isomorphic Partitioning Area Occupation Metrics Salomone Scheduling Allocation Policies Optimized Schedule
    41. 41. Schedule optimization <ul><li>Evaluates a scheduling for a target architecture… </li></ul><ul><li>Based on simply consideration </li></ul><ul><ul><li>Each SCoNo portion depends of </li></ul></ul><ul><ul><li>its biggest node </li></ul></ul><ul><ul><li>We must modify schedule if </li></ul></ul><ul><ul><li>exceeds area limit </li></ul></ul><ul><ul><li>If possible, we can save area and time anticipating loading of small different nodes of same SCoNo </li></ul></ul>
    42. 42. Project organization <ul><li>First phase: </li></ul><ul><ul><li>Development of the workflow </li></ul></ul><ul><ul><ul><li>Isomorph partitioning </li></ul></ul></ul><ul><ul><ul><li>Salomone </li></ul></ul></ul><ul><ul><ul><li>Area occupation metrics + optimization </li></ul></ul></ul><ul><ul><li>Benchmarks </li></ul></ul><ul><li>Second phase: </li></ul><ul><ul><li>Definition of the scheduler interfaces </li></ul></ul><ul><ul><li>Re-implementation of Salomone </li></ul></ul><ul><ul><li>Graphical representation </li></ul></ul>
    43. 43. Questions

    ×