3D-DRESD Polaris


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3D-DRESD Polaris

  1. 1. Polaris
  2. 2. <ul><li>A workflow to manage allocation and relocation of tasks in a reconfigurable architecture </li></ul><ul><li>Final goal: complete architecture (bitstreams) generation </li></ul>Polaris
  3. 3. Management of 2D Reconfiguration in a Reconfigurable System Massimo Morandi [email_address]
  4. 4. Outline <ul><li>Introduction </li></ul><ul><ul><li>Problem description </li></ul></ul><ul><ul><li>Project Goals and Contributions </li></ul></ul><ul><li>Project in details </li></ul><ul><ul><li>Phases </li></ul></ul><ul><ul><li>Results </li></ul></ul><ul><li>Future Work </li></ul>
  5. 5. Problem Description <ul><li>New Generation of FPGAs </li></ul><ul><ul><li>Virtex-4 and Virtex-5 </li></ul></ul><ul><ul><li>Allow bi-dimensional reconfiguration </li></ul></ul><ul><li>This permits to: </li></ul><ul><ul><li>Better exploit reconfigurable area </li></ul></ul><ul><ul><li>Obtain modules performance optimizations </li></ul></ul><ul><li>More complex management: </li></ul><ul><ul><li>Handle one more degree of freedom </li></ul></ul><ul><ul><li>Avoid more fragmentation </li></ul></ul><ul><ul><li>Perform good placement choices to keep low TRR </li></ul></ul><ul><ul><li>Keep acceptable intra-module routing paths </li></ul></ul>
  6. 6. Project Goals and Contributions <ul><li>Analyze effects of 2D reconfiguration </li></ul><ul><ul><li>New advantages </li></ul></ul><ul><ul><li>New problems </li></ul></ul><ul><li>Examine possible solutions to new problems </li></ul><ul><ul><li>Explore literature to find promising ideas </li></ul></ul><ul><ul><li>Evaluate those solutions in various scenarios </li></ul></ul><ul><li>Propose a new solution </li></ul><ul><ul><li>Combining ideas from literature with new ones </li></ul></ul><ul><ul><li>Obtaining good cost-quality tradeoff </li></ul></ul>
  7. 7. Setting and Advantages Definition <ul><li>Definition of the setting: </li></ul><ul><ul><li>2D self partial dynamical run-time reconfiguration </li></ul></ul><ul><li>Analysis of the advantages of 2D Reconfiguration </li></ul><ul><ul><li>In area usage and performance </li></ul></ul>
  8. 8. 2D Fragmentation Problem <ul><li>Analysis of the 2D-fragmentation problem </li></ul><ul><ul><li>Area generally more fragmented </li></ul></ul><ul><ul><li>Can nullify the area optimizations obtained </li></ul></ul>
  9. 9. Placement Decisions <ul><li>Analysis of 2D placement choices effects: </li></ul><ul><ul><li>Again, bad choices can lead to performance loss </li></ul></ul>
  10. 10. Allocation manager <ul><li>Definition of allocation manager desired features: </li></ul><ul><ul><li>Low TRR </li></ul></ul><ul><ul><li>Low management overhead </li></ul></ul><ul><ul><li>High routing efficiency </li></ul></ul><ul><ul><li>Low fragmentation </li></ul></ul><ul><li>Definition of allocation manager structure: </li></ul><ul><ul><li>Empty space manager </li></ul></ul><ul><ul><ul><li>Complete space </li></ul></ul></ul><ul><ul><ul><li>Heuristic selection </li></ul></ul></ul><ul><ul><li>Fitter </li></ul></ul><ul><ul><ul><li>General (FF,BL,BF,WF…) </li></ul></ul></ul><ul><ul><ul><li>Focused (FA,RA… ) </li></ul></ul></ul>
  11. 11. Most relevant works <ul><li>Maintain complete information on empty space: </li></ul><ul><ul><li>KAMER: </li></ul></ul><ul><ul><ul><li>Keep All Maximally Empty Rectangles </li></ul></ul></ul><ul><ul><ul><li>Apply a general fitting strategy </li></ul></ul></ul><ul><ul><li>CUR: </li></ul></ul><ul><ul><ul><li>Maintain the Countour of a Union of Rectangles </li></ul></ul></ul><ul><ul><ul><li>Apply a focused fitting strategy </li></ul></ul></ul><ul><li>Heuristically prune part of the information: </li></ul><ul><ul><li>KNER: </li></ul></ul><ul><ul><ul><li>Keep Non-overlapping Empty Rectangles </li></ul></ul></ul><ul><ul><ul><li>Apply a general fitting strategy </li></ul></ul></ul><ul><ul><li>2D-HASHING: </li></ul></ul><ul><ul><ul><li>Keep Non-ov. Empty Rectangles in optimized data structure </li></ul></ul></ul><ul><ul><ul><li>Apply (exclusively) a general fitting strategy </li></ul></ul></ul>
  12. 12. Evaluation and Proposed Approach <ul><li>Proposed Approach </li></ul><ul><ul><li>Heuristic (KNER-like) empty space manager, to keep low complexity for use in a self-reconfigurable system </li></ul></ul><ul><ul><li>Fitting strategy focused on minimizing routing paths, to maintain high performance of the reconfigurable system (chosen metric to minimize Manhattan distance) </li></ul></ul><ul><li>High placement quality => high complexity </li></ul><ul><li>Lowest compl. => no focused fitting (bad especially for routing) </li></ul>
  13. 13. Structure of the allocation manager <ul><li>Task, defined by: </li></ul><ul><ul><li>Arrival time, ASAP, (ALAP), H, W, Latency, Communicating Tasks </li></ul></ul><ul><ul><li>Hosted in a queue which also adds a pointer to the rectangle where it is placed </li></ul></ul><ul><li>Reconfigurable Device, represented as: </li></ul><ul><ul><li>Binary Tree structure, each node is a Rectangle, each leaf is an empty Rectangle. </li></ul></ul><ul><ul><li>Navigation trough pointers to left child, right child, next leaf and a function to find previous leaf (for bookkeeping after split or merge) </li></ul></ul><ul><li>Rectangle, defined by: </li></ul><ul><ul><li>X, Y, H, W </li></ul></ul><ul><ul><li>Initially one, (X,Y)=(0,0), H=FPGA Rows, W=FPGA Cols </li></ul></ul>
  14. 14. The Placement Algorithm
  15. 15. Experimental Results <ul><li>Benchmark of 100 randomly generated tasks: </li></ul><ul><ul><li>Size (5% to 25% of FPGA), randomly interconnected </li></ul></ul><ul><li>Execution time: 3x less than CUR, close to KNER </li></ul><ul><li>Communication cost: 3x less than KNER, close to CUR </li></ul><ul><li>Task Rejection Rate: all solutions quite close </li></ul>
  16. 16. Future Work <ul><li>Apply the proposed solution to self reconfiguration: </li></ul><ul><ul><li>Adapt the algorithm to run on the internal processor </li></ul></ul><ul><ul><li>Create a validation reconfigurable architecture </li></ul></ul><ul><ul><li>Integrate the architecture with relocation </li></ul></ul><ul><li>Tune the algorithm to improve results: </li></ul><ul><ul><li>Experiment techniques to reduce TRR </li></ul></ul><ul><ul><li>Try to optimize the code to have an algorithm with lower running time </li></ul></ul><ul><li>Evaluate other fitting strategies </li></ul>
  17. 17. Questions?
  18. 18. Relocation for 2D Reconfigurable Systems Marco Novati [email_address]
  19. 19. Project Outline <ul><li>Introduction </li></ul><ul><ul><li>Problem description </li></ul></ul><ul><ul><li>Project Goals </li></ul></ul><ul><li>Project in details </li></ul><ul><ul><li>Phases </li></ul></ul><ul><ul><li>Results </li></ul></ul><ul><li>What’s next </li></ul>
  20. 20. Problem Description <ul><li>Self Dynamical Runtime 2D Reconfiguration </li></ul><ul><ul><li>Xilinx Virtex-4 and Virtex-5 </li></ul></ul><ul><li>Relocation, different solutions </li></ul><ul><ul><li>Software </li></ul></ul><ul><ul><li>Hardware </li></ul></ul><ul><li>We chose an hardware solution </li></ul><ul><ul><li>BiRF Square </li></ul></ul>
  21. 21. Project Goals <ul><li>Study of the new FPGA Families </li></ul><ul><ul><li>Examination of Xilinx documentation on V4 and V5 </li></ul></ul><ul><li>Analysis of the new bitstream structure </li></ul><ul><ul><li>Generation of V4 and V5 bitstream </li></ul></ul><ul><li>Development of the new version of BiRF </li></ul><ul><ul><li>Implementation </li></ul></ul><ul><ul><li>Validation </li></ul></ul>
  22. 22. <ul><li>New Frame Addressing: </li></ul><ul><ul><li>Possibility of addressing rows and columns </li></ul></ul>Frame Addressing (1/2)
  23. 23. Frame Addressing (2/2)
  24. 24. New Parser
  25. 25. CRC Calculation <ul><li>Particular CRC value, used by Xilinx tools </li></ul><ul><li>Two version of BiRF Square: </li></ul><ul><ul><li>By using the “predefined” value </li></ul></ul><ul><ul><li>With actual CRC calculation </li></ul></ul><ul><li>An optimized algorithm has been used </li></ul>
  26. 26. Synthesis results <ul><li>On a Virtex-4 with speed grade -12 </li></ul><ul><ul><li>General purpose version: max frequency of 160 MHz </li></ul></ul><ul><ul><li>Specific version: max frequency of 290 Mhz </li></ul></ul>
  27. 27. Target Device
  28. 28. Validation Architecture
  29. 29. Results (1/2) <ul><li>BiRF Square </li></ul><ul><ul><li>Permits apply relocation in a self partially and dynamically 2D-reconfigurable system </li></ul></ul><ul><ul><li>The occupation ratio is relatively small </li></ul></ul><ul><ul><li>Frequency more than acceptable </li></ul></ul><ul><ul><li>Reduction of internal memory requirements </li></ul></ul>
  30. 30. Results (2/2) <ul><li>Throughput of 7,3 MB/s: </li></ul><ul><ul><li>A total configuration file size is about 1 MB </li></ul></ul><ul><ul><li>Considering an architecture: </li></ul></ul><ul><ul><ul><li>1/3 of the area as fixed part </li></ul></ul></ul><ul><ul><ul><li>2/3 as reconfigurable part with 6 slots </li></ul></ul></ul><ul><ul><li>With such hypothesis </li></ul></ul><ul><ul><ul><li>Size of a partial bitstream will be about 110 KB </li></ul></ul></ul><ul><ul><ul><li>Relocation time of about 15 ms </li></ul></ul></ul>
  31. 31. What’s Next <ul><li>Future improvements: </li></ul><ul><ul><li>Direct access to the memory (DMA) </li></ul></ul><ul><ul><ul><li>Direct manipulation of the bitstream </li></ul></ul></ul><ul><ul><ul><li>Portability </li></ul></ul></ul><ul><ul><li>Integration with ICAP </li></ul></ul><ul><ul><ul><li>Elimination of the relocation overhead </li></ul></ul></ul><ul><ul><ul><li>Relocation time << reconfiguration time </li></ul></ul></ul><ul><li>Future work: </li></ul><ul><ul><li>Provide a simulation framework to monitor the reconfigurable system evolution and to evaluate different choices </li></ul></ul><ul><li>The final goal: </li></ul><ul><ul><li>Creation of a real architecture that exploits self partial and dynamical 2D-reconfiguration,with relocation </li></ul></ul>
  32. 32. Questions