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Ruud Haring - Modeling Complex Systems

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Slides presented by Ruud Haring, at the 2011 Urban Systems Symposium. http://urbansystemssymposium.org/

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Ruud Haring - Modeling Complex Systems

  1. 1. Chip design as a metaphor -- providing services to the millions Ruud Haring, IBM Research
  2. 2. <ul><li>A well-defined set of functions , performed by </li></ul><ul><li>100s of millions of transistors </li></ul><ul><li>each requiring services </li></ul><ul><ul><li>power supply, ground </li></ul></ul><ul><li>each with individual connections </li></ul><ul><li>Constraints </li></ul><ul><li>area </li></ul><ul><li>timing </li></ul><ul><li>power distribution / noise </li></ul><ul><li>power dissipation </li></ul><ul><li>resources </li></ul><ul><ul><li>routing channels for interconnections </li></ul></ul><ul><li>manufacturability , testability </li></ul><ul><li>… .. </li></ul>A chip design is a complex system
  3. 3. Chip Design – modeling approaches <ul><li>Levels of abstraction </li></ul><ul><li>transistors </li></ul><ul><ul><li>solid state physics, materials science </li></ul></ul><ul><ul><li>abstracted to electrical characteristics: current/voltage/capacitance </li></ul></ul><ul><li>logic gates: and, or, not, latch </li></ul><ul><ul><li>digital 0 and 1 </li></ul></ul><ul><ul><li>physical abstraction: small box with pins + area, power, delay </li></ul></ul><ul><li>units: arithmetic unit, memory array </li></ul><ul><ul><li>large set of interconnected logic gates or transistors </li></ul></ul><ul><ul><li>well characterized sub-function </li></ul></ul><ul><ul><ul><li>captured in logic design language : C <= (A + B) when ( D=1 ) else (not E); </li></ul></ul></ul><ul><ul><li>physical abstraction: bigger box with pins + area, power, delays, blockages </li></ul></ul><ul><li>chip: microprocessor, memory chip, …. </li></ul><ul><ul><li>interconnected units </li></ul></ul><ul><ul><li>has well defined abstraction for software team </li></ul></ul><ul><ul><ul><li>register set </li></ul></ul></ul><ul><ul><ul><li>programming guide </li></ul></ul></ul>
  4. 4. Chip Design team -- use of the abstractions <ul><li>Technologists </li></ul><ul><ul><li>transistors (lithography, charcteristics) </li></ul></ul><ul><ul><li>interconnect levels </li></ul></ul><ul><ul><li>device modelers – I/V curves </li></ul></ul><ul><ul><li>manufacturability rules </li></ul></ul><ul><li>Library designers </li></ul><ul><ul><li>create logic gates, arrays + defining rules (pins, area, delay, …) </li></ul></ul><ul><li>Architects </li></ul><ul><ul><li>overall function of the chip, in the system. Try to be smarter… </li></ul></ul><ul><ul><li>logic abstraction for software team </li></ul></ul><ul><li>Logic designers </li></ul><ul><ul><li>implement architecture -- at digital (0/1) level </li></ul></ul><ul><ul><li>verification team keeps them honest << software team </li></ul></ul><ul><li>Physical designers </li></ul><ul><ul><li>floorplanning </li></ul></ul><ul><ul><li>placing logic, routing interconnects, distributing power, clocks -- per unit / per chip </li></ul></ul><ul><ul><li>timing closure -- per unit / per chip </li></ul></ul><ul><ul><li>noise </li></ul></ul><ul><ul><li>rules – checking – rules – checking … more checking… </li></ul></ul><ul><li>Fabricators </li></ul><ul><ul><li>generate masks from layout </li></ul></ul><ul><ul><li>lithography/implant/deposit/etch/polish/plate … 100s of steps for 50 or so layers </li></ul></ul><ul><li>Testers </li></ul><ul><ul><li>weed out manufacturing defects </li></ul></ul><ul><ul><li>tell us what went wrong … </li></ul></ul><ul><li>Project managers, other managers… </li></ul>
  5. 5. Chip Design as a metaphor for an urban system ? <ul><li>Chip designers can handle the complexity </li></ul><ul><ul><li>because different teams can work with different levels of abstraction </li></ul></ul><ul><ul><li>… while checking tools assure that their level is consistent with the whole. </li></ul></ul><ul><ul><li>because the abstractions fit the math (or the math fits the abstractions?) </li></ul></ul><ul><ul><li>because the software tools fit the math/abstractions and rules/checkers </li></ul></ul><ul><ul><li>because nature is – mostly – obliging the abstractions </li></ul></ul><ul><li>It is “easy” because… </li></ul><ul><li>transistors do not have opinions… </li></ul><ul><li>signals only have a single place (or few fixed places) to go </li></ul><ul><ul><li>over dedicated wires </li></ul></ul><ul><li>no eminent domain problems </li></ul><ul><li>10 or so vertically stacked, non-intersecting levels of signal traffic </li></ul><ul><ul><li>and no transistor minds living under them </li></ul></ul><ul><ul><li>or… inverted view: no signal minds doing all their traveling underground. </li></ul></ul>

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