Gpu and The Brick Wall

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GPU programing
The Brick Wall -- UC Berkeley's View
Power Wall: power expensive, transistors free
Memory Wall: Memory slow, multiplies fast ILP Wall: diminishing returns on more ILP HW

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  • NVIDIA planned to put 512 PEs into a single GPU, but the GTX480 turns out to have 480 PEs.
  • GPU can achieve 10x performance over CPU. 
  • Notice the third place is PowerXCell. Rmax is the performance of Linpack benchmark. Rpeak is the raw performance of the machine.
  • This gap is narrowed by multi-core CPUs.
  • Comparing raw performance is less interesting.
  • The area breakdown is an approximation, but it is good enough to see the trend.
  • The size of L3 in high end and low end CPUs are quite different.
  • This break down is also an approximation.
  • Numbers are based on Intel Nehalem at 45nm and the presentation of Bill Dally.
  • More registers are required to store the contexts of threads.
  • Hiding memory latency by multi-threading. The Cell uses a relatively static approach. The overlapping of computation and DMA transfer is explicitly specified by programmer.
  • Fine-grained multi-threading can keep the PEs busy even the program has little ILP.
  • The cache can still help.
  • The address assignment and translation is done dynamically by hardware.
  • The vector core should be larger than scalar core.
  • From scalar to vector.
  • From vector to threads.
  • Warp can be grouped at run time by hardware. In this case it will be transparent to the programmer.
  • The NVIDIA Fermi PE can do int and fp.
  • We have ignored some architectural features of Fermi.  Noticeably the interconnection network is not discussed here. 
  • These features are summarized by the paper of Michael Garland and David Kirk.
  • The vector program use SSE as example. However, the "incps" is not an SSE instruction. It is used here to represent incrementation of the vector.
  • Each thread uses its ID to locate its working data set.
  • The scheduler tries to maintain load balancing among SMs.
  • Numbers taken from an old paper on G80 architecture, but it should be similar to the GF100 architecture.
  • The old architecture has 16 banks.
  • It is a trend to use threads to hide vector width. The OpenCL applies the same programming model.
  • It is arguable whether working on threads is more productive.
  • This example assumes the two warp schedulers are decoupled. It is possible that they are coupled together, at the cost of hardware complexity.
  • Assume the register file has one read port. The register file may need two read port to support instructions with 3 source operands, e.g. the Fused Multiply Add (FMA).
  • 5 issue VLIW.
  • The atomic unit is helpful in voting operation, e.g. histogram. 
  • The figure is taken from 8800 GPU. See the paper of Samuel Williams for more detail.
  • The number is obtained in 8800 GPU.
  • The latency hiding is addressed in the PhD thesis of Samuel Williams.
  • Gpu and The Brick Wall

    1. 1. Graphics Processing Unit (GPU) Architecture and Programming TU/e 5kk73 Zhenyu Ye Bart Mesman Henk Corporaal 2010-11-08
    2. 2. Today's Topics <ul><ul><li>GPU architecture </li></ul></ul><ul><ul><li>GPU programming </li></ul></ul><ul><ul><li>GPU micro-architecture </li></ul></ul><ul><ul><li>Performance optimization and model </li></ul></ul><ul><ul><li>Trends </li></ul></ul>
    3. 3. Today's Topics <ul><ul><li>GPU architecture </li></ul></ul><ul><ul><li>GPU programming </li></ul></ul><ul><ul><li>GPU micro-architecture </li></ul></ul><ul><ul><li>Performance optimization and model </li></ul></ul><ul><ul><li>Trends </li></ul></ul>
    4. 4. System Architecture
    5. 5. GPU Architecture NVIDIA Fermi, 512 Processing Elements (PEs)
    6. 6. What Can It Do? Render triangles. NVIDIA GTX480 can render 1.6 billion triangles per second!
    7. 7. General Purposed Computing ref:  http://www.nvidia.com/object/tesla_computing_solutions.html
    8. 8. The Vision of NVIDIA <ul><li>&quot;Within the next few years, there will be single-chip graphics devices more powerful and versatile than any graphics system that has ever been built, at any price.&quot;  </li></ul><ul><li>-- David Kirk, NVIDIA,  1998 </li></ul>
    9. 9. Single-Chip GPU v.s. Fastest Super Computers ref:  http://www.llnl.gov/str/JanFeb05/Seager.html
    10. 10. Top500 Super Computer in June 2010
    11. 11. GPU Will Top the List in Nov 2010
    12. 12. The Gap Between CPU and GPU ref: Tesla GPU Computing Brochure
    13. 13. GPU Has 10x Comp Density Given the same chip area , the achievable performance of GPU is 10x higher than that of CPU.
    14. 14. Evolution of Intel Pentium Pentium I Pentium II Pentium III Pentium IV Chip area breakdown Q: What can you observe? Why?
    15. 15. Extrapolation of Single Core CPU If we extrapolate the trend, in a few generations, Pentium will look like: Of course, we know it did not happen.  Q: What happened instead? Why?
    16. 16. Evolution of Multi-core CPUs Penryn Bloomfield Gulftown Beckton Chip area breakdown Q: What can you observe? Why?
    17. 17. Let's Take a Closer Look Less than 10% of total chip area is used for the real execution. Q: Why?
    18. 18. The Memory Hierarchy Notes on Energy at 45nm:  64-bit Int ADD takes about 1 pJ. 64-bit FP FMA takes about 200 pJ. It seems we can not further increase the computational density.
    19. 19. The Brick Wall -- UC Berkeley's View Power Wall : power expensive, transistors free Memory Wall : Memory slow, multiplies fast ILP Wall : diminishing returns on more ILP HW David Patterson, &quot;Computer Architecture is Back - The Berkeley View of the Parallel Computing Research Landscape&quot;, Stanford EE Computer Systems Colloquium, Jan 2007, link
    20. 20. The Brick Wall -- UC Berkeley's View Power Wall : power expensive, transistors free Memory Wall : Memory slow, multiplies fast ILP Wall : diminishing returns on more ILP HW Power Wall + Memory Wall + ILP Wall = Brick Wall David Patterson, &quot;Computer Architecture is Back - The Berkeley View of the Parallel Computing Research Landscape&quot;, Stanford EE Computer Systems Colloquium, Jan 2007, link
    21. 21. How to Break the Brick Wall? Hint: how to exploit the parallelism inside the application?
    22. 22. Step 1: Trade Latency with Throughput Hind the memory latency through fine-grained interleaved threading.
    23. 23. Interleaved Multi-threading
    24. 24. Interleaved Multi-threading <ul><li>The granularity of interleaved multi-threading: </li></ul><ul><ul><li>100 cycles : hide off-chip memory latency </li></ul></ul><ul><ul><li>10 cycles : + hide cache latency </li></ul></ul><ul><ul><li>1 cycle : + hide branch latency, instruction dependency </li></ul></ul>
    25. 25. Interleaved Multi-threading <ul><li>The granularity of interleaved multi-threading: </li></ul><ul><ul><li>100 cycles: hide off-chip memory latency </li></ul></ul><ul><ul><li>10 cycles: + hide cache latency </li></ul></ul><ul><ul><li>1 cycle: + hide branch latency, instruction dependency </li></ul></ul><ul><li>Fine-grained interleaved multi-threading: </li></ul><ul><li>Pros : ? </li></ul><ul><li>Cons : ? </li></ul>
    26. 26. Interleaved Multi-threading <ul><li>The granularity of interleaved multi-threading: </li></ul><ul><ul><li>100 cycles: hide off-chip memory latency </li></ul></ul><ul><ul><li>10 cycles: + hide cache latency </li></ul></ul><ul><ul><li>1 cycle: + hide branch latency, instruction dependency </li></ul></ul><ul><li>Fine-grained interleaved multi-threading: </li></ul><ul><li>Pros : remove branch predictor, OOO scheduler, large cache </li></ul><ul><li>Cons : register pressure, etc. </li></ul>
    27. 27. Fine-Grained Interleaved Threading Pros:  reduce cache size, no branch predictor,  no OOO scheduler Cons:  register pressure, thread scheduler, require huge parallelism Without and with fine-grained interleaved threading
    28. 28. HW Support Register file supports zero overhead context switch between interleaved threads.
    29. 29. Can We Make Further Improvement? <ul><li>Reducing large cache gives 2x computational density. </li></ul><ul><li>Q: Can we make further improvements? </li></ul>Hint: We have only utilized thread level parallelism (TLP) so far.
    30. 30. Step 2: Single Instruction Multiple Data SSE has 4 data lanes GPU has 8/16/24/... data lanes GPU uses wide SIMD: 8/16/24/... processing elements (PEs) CPU uses short SIMD: usually has vector width of 4.
    31. 31. Hardware Support Supporting interleaved threading + SIMD execution
    32. 32. Single Instruction Multiple Thread (SIMT) Hide vector width using scalar threads.
    33. 33. Example of SIMT Execution Assume 32 threads are grouped into one warp.
    34. 34. Step 3: Simple Core The Stream Multiprocessor (SM) is a light weight core compared to IA core. Light weight PE: Fused Multiply Add (FMA) SFU: Special Function Unit
    35. 35. NVIDIA's Motivation of Simple Core &quot;This [multiple IA-core] approach is analogous to trying to build an airplane by putting wings on a train.&quot; --Bill Dally, NVIDIA
    36. 36. Review: How Do We Reach Here? NVIDIA Fermi, 512 Processing Elements (PEs)
    37. 37. Throughput Oriented Architectures <ul><ul><li>Fine-grained interleaved threading (~2x comp density) </li></ul></ul><ul><ul><li>SIMD/SIMT (>10x comp density) </li></ul></ul><ul><ul><li>Simple core (~2x comp density) </li></ul></ul><ul><li>Key architectural features of throughput oriented processor. </li></ul>ref: Michael Garland. David B. Kirk, &quot;Understanding throughput-oriented architectures&quot;, CACM 2010. ( link )
    38. 38. Today's Topics <ul><ul><li>GPU architecture </li></ul></ul><ul><ul><li>GPU programming </li></ul></ul><ul><ul><li>GPU micro-architecture </li></ul></ul><ul><ul><li>Performance optimization and model </li></ul></ul><ul><ul><li>Trends </li></ul></ul>
    39. 39. CUDA Programming Massive number (>10000) of light-weight threads.
    40. 40. Express Data Parallelism in Threads  <ul><li>Compare thread program with vector program. </li></ul>
    41. 41. Vector Program <ul><li>Scalar program </li></ul><ul><li>  </li></ul><ul><li>float A[4][8]; </li></ul><ul><li>do-all(i=0;i<4;i++){ </li></ul><ul><li>    do-all(j=0;j<8;j++){ </li></ul><ul><li>        A[i][j]++; </li></ul><ul><li>     } </li></ul><ul><li>} </li></ul><ul><li>Vector program (vector width of 8) </li></ul><ul><li>float A[4][8]; </li></ul><ul><li>do-all(i=0;i<4;i++){ </li></ul><ul><li>     movups xmm0, [ &A[i][0] ] </li></ul><ul><li>     incps xmm0 </li></ul><ul><li>     movups [ &A[i][0] ], xmm0 </li></ul><ul><li>} </li></ul><ul><li>  </li></ul>Vector width is exposed to programmers.
    42. 42. CUDA Program <ul><li>Scalar program </li></ul><ul><li>  </li></ul><ul><li>float A[4][8]; </li></ul><ul><li>do-all(i=0;i<4;i++) { </li></ul><ul><li>    do-all(j=0;j<8;j++) { </li></ul><ul><li>        A[i][j]++; </li></ul><ul><li>     } </li></ul><ul><li>} </li></ul><ul><li>CUDA program </li></ul><ul><li>float A[4][8]; </li></ul><ul><li>  </li></ul><ul><li>kernelF<<<(4,1),(8,1)>>>(A); </li></ul><ul><li>  </li></ul><ul><li>__device__    kernelF(A){ </li></ul><ul><li>     i = blockIdx.x; </li></ul><ul><li>     j = threadIdx.x; </li></ul><ul><li>    A[i][j]++; </li></ul><ul><li>} </li></ul><ul><li>  </li></ul><ul><ul><li>CUDA program expresses data level parallelism (DLP) in terms of thread level parallelism (TLP). </li></ul></ul><ul><ul><li>Hardware converts TLP into DLP at run time. </li></ul></ul>
    43. 43. Two Levels of Thread Hierarchy <ul><li>kernelF<<<(4,1),(8,1)>>>(A); </li></ul><ul><li>  </li></ul><ul><li>__device__    kernelF(A){ </li></ul><ul><li>     i = blockIdx.x; </li></ul><ul><li>     j = threadIdx.x; </li></ul><ul><li>    A[i][j]++; </li></ul><ul><li>} </li></ul><ul><li>  </li></ul>
    44. 44. Multi-dimension Thread and Block ID <ul><li>kernelF<<<(2,2),(4,2)>>>(A); </li></ul><ul><li>  </li></ul><ul><li>__device__    kernelF(A){ </li></ul><ul><li>     i = blockDim.x * blockIdx.y </li></ul><ul><li>         + blockIdx.x; </li></ul><ul><li>     j = threadDim.x * threadIdx.y </li></ul><ul><li>         + threadIdx.x; </li></ul><ul><li>    A[i][j]++; </li></ul><ul><li>} </li></ul><ul><li>  </li></ul>Both grid and thread block can have two dimensional index.
    45. 45. Scheduling Thread Blocks on SM Example: Scheduling 4 thread blocks on 3 SMs.
    46. 46. Executing Thread Block on SM <ul><li>kernelF<<<(2,2), (4,2) >>>(A); </li></ul><ul><li>  </li></ul><ul><li>__device__    kernelF(A){ </li></ul><ul><li>     i = blockDim.x * blockIdx.y </li></ul><ul><li>         + blockIdx.x; </li></ul><ul><li>     j = threadDim.x * threadIdx.y </li></ul><ul><li>         + threadIdx.x; </li></ul><ul><li>    A[i][j]++; </li></ul><ul><li>} </li></ul><ul><li>  </li></ul>Executed on machine with width of 4: Executed on machine with width of 8: Notes: the number of Processing Elements (PEs) is transparent to programmer.
    47. 47. Multiple Levels of Memory Hierarchy Name Cache? cycle read-only? Global L1/L2 200~400 (cache miss) R/W Shared No 1~3 R/W Constant Yes 1~3 Read-only Texture Yes ~100 Read-only Local L1/L2 200~400 (cache miss) R/W
    48. 48. Explicit Management of Shared Mem Shared memory is frequently used to exploit locality.
    49. 49. Shared Memory and Synchronization kernelF<<<(1,1),(16,16)>>>(A);   __device__    kernelF(A){      __shared__ smem[16][16]; //allocate smem      i = threadIdx.y;      j = threadIdx.x;      smem[i][j] = A[i][j];      __sync();      A[i][j] = ( smem[i-1][j-1]                    + smem[i-1][j]                    ...                    + smem[i+1][i+1] ) / 9; }   Example: average filter with 3x3 window 3x3 window on image Image data in DRAM
    50. 50. Shared Memory and Synchronization kernelF<<<(1,1),(16,16)>>>(A);   __device__    kernelF(A){      __shared__ smem[16][16];      i = threadIdx.y;      j = threadIdx.x;      smem[i][j] = A[i][j]; // load to smem      __sync(); // thread wait at barrier      A[i][j] = ( smem[i-1][j-1]                    + smem[i-1][j]                    ...                    + smem[i+1][i+1] ) / 9; }   Example: average filter over 3x3 window 3x3 window on image Stage data in shared mem
    51. 51. Shared Memory and Synchronization kernelF<<<(1,1),(16,16)>>>(A);   __device__    kernelF(A){      __shared__ smem[16][16];      i = threadIdx.y;      j = threadIdx.x;      smem[i][j] = A[i][j];      __sync(); // every thread is ready      A[i][j] = ( smem[i-1][j-1]                    + smem[i-1][j]                    ...                    + smem[i+1][i+1] ) / 9; }   Example: average filter over 3x3 window 3x3 window on image all threads finish the load
    52. 52. Shared Memory and Synchronization kernelF<<<(1,1),(16,16)>>>(A);   __device__    kernelF(A){      __shared__ smem[16][16];      i = threadIdx.y;      j = threadIdx.x;      smem[i][j] = A[i][j];      __sync();      A[i][j] = ( smem[i-1][j-1]                    + smem[i-1][j]                    ...                    + smem[i+1][i+1] ) / 9; }   Example: average filter over 3x3 window 3x3 window on image Start computation
    53. 53. Programmers Think in Threads Q: Why make this hassle?
    54. 54. Why Use Thread instead of Vector? <ul><li>Thread Pros: </li></ul><ul><ul><li>Portability . Machine width is transparent in ISA. </li></ul></ul><ul><ul><li>Productivity . Programmers do not need to take care the vector width of the machine. </li></ul></ul><ul><li>Thread Cons: </li></ul><ul><ul><li>Manual sync . Give up lock-step within vector. </li></ul></ul><ul><ul><li>Scheduling of thread could be inefficient. </li></ul></ul><ul><ul><li>Debug . &quot;Threads considered harmful&quot;. Thread program is notoriously hard to debug.   </li></ul></ul>
    55. 55. Features of CUDA <ul><ul><li>Programmers explicitly express DLP in terms of TLP. </li></ul></ul><ul><ul><li>Programmers explicitly manage memory hierarchy. </li></ul></ul><ul><ul><li>etc. </li></ul></ul>
    56. 56. Today's Topics <ul><ul><li>GPU architecture </li></ul></ul><ul><ul><li>GPU programming </li></ul></ul><ul><ul><li>GPU micro-architecture </li></ul></ul><ul><ul><li>Performance optimization and model </li></ul></ul><ul><ul><li>Trends </li></ul></ul>
    57. 57. Micro-architecture GF100 micro-architecture
    58. 58. HW Groups Threads Into Warps Example: 32 threads per warp
    59. 59. Example of Implementation Note: NVIDIA may use a more complicated implementation.
    60. 60. Example <ul><li>Program Address : Inst </li></ul><ul><li>0x0004 : add r0, r1, r2 </li></ul><ul><li>0x0008 : sub r3, r4, r5 </li></ul>Assume warp 0 and warp 1 are scheduled for execution.
    61. 61. Read Src Op <ul><li>Program Address: Inst </li></ul><ul><li>0x0004: add r0, r1 , r2 </li></ul><ul><li>0x0008: sub r3, r4 , r5 </li></ul>Read source operands: r1 for warp 0 r4 for warp 1
    62. 62. Buffer Src Op <ul><li>Program Address: Inst </li></ul><ul><li>0x0004: add r0, r1 , r2 </li></ul><ul><li>0x0008: sub r3, r4 , r5 </li></ul>Push ops to op collector: r1 for warp 0 r4 for warp 1
    63. 63. Read Src Op <ul><li>Program Address: Inst </li></ul><ul><li>0x0004: add r0, r1, r2 </li></ul><ul><li>0x0008: sub r3, r4, r5 </li></ul>Read source operands: r2 for warp 0 r5 for warp 1
    64. 64. Buffer Src Op <ul><li>Program Address: Inst </li></ul><ul><li>0x0004: add r0, r1, r2 </li></ul><ul><li>0x0008: sub r3, r4, r5 </li></ul>Push ops to op collector: r2 for warp 0 r5 for warp 1
    65. 65. Execute <ul><li>Program Address: Inst </li></ul><ul><li>0x0004: add r0, r1, r2 </li></ul><ul><li>0x0008: sub r3, r4, r5 </li></ul>Compute the first 16 threads in the warp.
    66. 66. Execute <ul><li>Program Address: Inst </li></ul><ul><li>0x0004: add r0, r1, r2 </li></ul><ul><li>0x0008: sub r3, r4, r5 </li></ul>Compute the last 16 threads in the warp.
    67. 67. Write back <ul><li>Program Address: Inst </li></ul><ul><li>0x0004: add r0 , r1, r2 </li></ul><ul><li>0x0008: sub r3 , r4, r5 </li></ul>Write back: r0 for warp 0 r3 for warp 1
    68. 68. Other High Performance GPU <ul><ul><li>ATI Radeon 5000 series. </li></ul></ul>
    69. 69. ATI Radeon 5000 Series Architecture
    70. 70. Radeon SIMD Engine <ul><ul><li>16 Stream Cores (SC) </li></ul></ul><ul><ul><li>Local Data Share </li></ul></ul>
    71. 71. VLIW Stream Core (SC)
    72. 72. Local Data Share (LDS)
    73. 73. Today's Topics <ul><ul><li>GPU architecture </li></ul></ul><ul><ul><li>GPU programming </li></ul></ul><ul><ul><li>GPU micro-architecture </li></ul></ul><ul><ul><li>Performance optimization and model </li></ul></ul><ul><ul><li>Trends </li></ul></ul>
    74. 74. Performance Optimization <ul><li>Optimizations on memory latency tolerance </li></ul><ul><ul><li>Reduce register pressure </li></ul></ul><ul><ul><li>Reduce shared memory pressure </li></ul></ul><ul><li>   </li></ul><ul><li>Optimizations on memory bandwidth </li></ul><ul><ul><li>Global memory coalesce </li></ul></ul><ul><ul><li>Avoid shared memory bank conflicts </li></ul></ul><ul><ul><li>Grouping byte access </li></ul></ul><ul><ul><li>Avoid Partition camping </li></ul></ul><ul><li>  </li></ul><ul><li>Optimizations on computation efficiency </li></ul><ul><ul><li>Mul/Add balancing </li></ul></ul><ul><ul><li>Increase floating point proportion  </li></ul></ul><ul><li>  </li></ul><ul><li>Optimizations on operational intensity </li></ul><ul><ul><li>Use tiled algorithm </li></ul></ul><ul><ul><li>Tuning thread granularity </li></ul></ul>
    75. 75. Performance Optimization <ul><li>Optimizations on memory latency tolerance </li></ul><ul><ul><li>Reduce register pressure </li></ul></ul><ul><ul><li>Reduce shared memory pressure </li></ul></ul><ul><li>   </li></ul><ul><li>Optimizations on memory bandwidth </li></ul><ul><ul><li>Global memory coalesce </li></ul></ul><ul><ul><li>Avoid shared memory bank conflicts </li></ul></ul><ul><ul><li>Grouping byte access </li></ul></ul><ul><ul><li>Avoid Partition camping </li></ul></ul><ul><li>  </li></ul><ul><li>Optimizations on computation efficiency </li></ul><ul><ul><li>Mul/Add balancing </li></ul></ul><ul><ul><li>Increase floating point proportion  </li></ul></ul><ul><li>  </li></ul><ul><li>Optimizations on operational intensity </li></ul><ul><ul><li>Use tiled algorithm </li></ul></ul><ul><ul><li>Tuning thread granularity </li></ul></ul>
    76. 76. Shared Mem Contains Multiple Banks
    77. 77. Compute Capability Need arch info to perform optimization. ref: NVIDIA, &quot;CUDA C Programming Guide&quot;, ( link )
    78. 78. Shared Memory (compute capability 2.x) without bank conflict: with bank conflict:
    79. 79. Performance Optimization <ul><li>Optimizations on memory latency tolerance </li></ul><ul><ul><li>Reduce register pressure </li></ul></ul><ul><ul><li>Reduce shared memory pressure </li></ul></ul><ul><li>   </li></ul><ul><li>Optimizations on memory bandwidth </li></ul><ul><ul><li>Global memory alignment and coalescing </li></ul></ul><ul><ul><li>Avoid shared memory bank conflicts </li></ul></ul><ul><ul><li>Grouping byte access </li></ul></ul><ul><ul><li>Avoid Partition camping </li></ul></ul><ul><li>  </li></ul><ul><li>Optimizations on computation efficiency </li></ul><ul><ul><li>Mul/Add balancing </li></ul></ul><ul><ul><li>Increase floating point proportion  </li></ul></ul><ul><li>  </li></ul><ul><li>Optimizations on operational intensity </li></ul><ul><ul><li>Use tiled algorithm </li></ul></ul><ul><ul><li>Tuning thread granularity </li></ul></ul>
    80. 80. Global Memory In Off-Chip DRAM <ul><li>Address space is interleaved among multiple channels. </li></ul>
    81. 81. Global Memory
    82. 82. Global Memory
    83. 83. Global Memory
    84. 84. Roofline Model Identify performance bottleneck:  computation bound v.s. bandwidth bound
    85. 85. Optimization Is Key for Attainable Gflops/s
    86. 86. Computation, Bandwidth, Latency <ul><li>Illustrating three bottlenecks in the Roofline model. </li></ul>
    87. 87. Today's Topics <ul><ul><li>GPU architecture </li></ul></ul><ul><ul><li>GPU programming </li></ul></ul><ul><ul><li>GPU micro-architecture </li></ul></ul><ul><ul><li>Performance optimization and model </li></ul></ul><ul><ul><li>Trends </li></ul></ul>
    88. 88. Trends <ul><li>Coming architectures: </li></ul><ul><ul><li>Intel's Larabee successor: Many Integrated Core (MIC) </li></ul></ul><ul><ul><li>CPU/GPU fusion, Intel Sandy Bridge, AMD Llano. </li></ul></ul>
    89. 89. Intel Many Integrated Core (MIC) 32 core version of MIC:
    90. 90. Intel Sandy Bridge <ul><li>Highlight: </li></ul><ul><ul><li>Reconfigurable shared L3 for CPU and GPU </li></ul></ul><ul><ul><li>Ring bus </li></ul></ul>
    91. 91. Sandy Bridge's New CPU-GPU interface  ref: &quot;Intel's Sandy Bridge Architecture Exposed&quot;, from Anandtech, ( link )
    92. 92. Sandy Bridge's New CPU-GPU interface  ref: &quot;Intel's Sandy Bridge Architecture Exposed&quot;, from Anandtech, ( link )
    93. 93. AMD Llano Fusion APU (expt. Q3 2011) <ul><li>Notes: </li></ul><ul><ul><li>CPU and GPU are not sharing cache? </li></ul></ul><ul><ul><li>Unknown interface between CPU/GPU </li></ul></ul>
    94. 94. GPU Research in ES Group <ul><li>GPU research in the Electronic Systems group. </li></ul><ul><li>http://www.es.ele.tue.nl/~gpuattue/ </li></ul>

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