Adaptive Wireless Sensor Networks: A System Design Approach to Adaptive Reliability Rachit Agarwal∗† , Emanuel M. Popovici∗ and Brendan O’Flynn† ∗ Department of Microelectronic Engineering, University College Cork, Cork, Ireland † MicroelectronicsApplication Integration Group, Tyndall National Institute, Cork, Ireland Email: email@example.com, firstname.lastname@example.org, brendan.oﬂynn@tyndall.ie Abstract— Reliable Data Transport is an important facet of Finally, from a software engineering standpoint, diversedependability and quality of service in Wireless Sensor Networks routing layers add more challenges. Since motes are resource(WSN). In such networks, erroneous packets can be recovered constrained, applications tend to make heavy use of customi-by two basic methods, Automatic Repeat Request (ARQ) and For-ward Error Correction (FEC). Retransmission being an expensive sation and cross-layer optimisations.operation in terms of energy, FECs are generally looked for While the fourth type of problems can be eradicated by hav-correcting erroneous packets. Diversiﬁed features of WSN nodes ing a software interface between transceiver and informationand applications require ﬂexible loss recovery in order to further processing unit (hardware/software)1 , an application drivenoptimize energy efﬁciency. This paper proposes a dynamically design and implementation methodology provides a solutionadaptable FEC scheme based on Universal Reed Solomon de-coder for reliability in sensor networks having diversiﬁed sensing for third type of problems. It is the ﬁrst and second type ofand transmitting nodes. A system design approach is discussed problems which are majorly concentrated on in this paper.to explore the design space with efﬁciency/ﬂexibility trade-off To extend our discussion, let us broadly divide WSNand a Dynamic Partitioning Module has been presented for systems in three categories based on system and applicationoptimum performance of the system. The developed system infers constraints: [Type I]: Resource Constrained, [Type II]: Energythe best error correcting scheme and partitioning scheme foroptimal performance based on the the channel conditions and Constrained and [Type III]: Throughput Constrained Systemssystem/network constraints. The results of implementation of the ARQ: The advantages of ARQ are relative simplicity,proposed system on wireless motes show that up to 56% of the optimal throughput and no overhead in a non-error situation.power savings can be achieved with less than 4% overhead of The main disadvantages of ARQ are the retransmitting coststhe running system costs. in terms of huge delays and energy when an error does occur. In wireless networks, transmitting a packet is one of the most I. I NTRODUCTION costly operations to perform by a node. Therefore, sending Wireless Sensor Networks (WSN) have a wide range of packets or retransmitting has to be done as few times aspotential applications, including security and surveillance, possible.control, actuation and maintenance of complex systems, and FEC: The advantage of FEC is that there are no time delaysﬁne-grain monitoring of indoor and outdoor environments. in the message ﬂows (or a bounded small delay, consideringMany of these applications (medical, surveillance, monitoring) the encoding and decoding operations), because there are norequire all the data to be transmitted with high reliability. retransmissions. A disadvantage is that packets can get lost Challenges to achieving reliability on WSN can be divided when the error correcting code is not strong enough to correctinto four main categories. The ﬁrst problems are related to the error.the wireless communication. Channels in WSN are often Adaptive Universal FEC (AuFEC): An open problem hasunreliable with high probability of introducing bursts of errors. been discussed in , which is reproduced here,Weak correlation between quality and distance, hidden termi- ”... most reliability protocols use a single and identical loss-nal problems, and dynamic change of connectivity complicate recovery algorithm for all nodes and applications, ..... How-the situation further. ever, the nodes and the applications may consist of diversiﬁed Problems due to diverse applications and sensory data type features and priorities, which require ﬂexible loss recovery inconstitute to the second category of problems. Sink node is re- order to optimise energy efﬁciency. ...”.quired to interact with several transmitting nodes, each or some This is similar to ﬁrst and second type of problems discussedof them having different kind of sensory data. In addition, earlier. Such a scenario is shown in Figure 1. A solution to thismigration of the system over various applications impose more is to have an adaptive and universal codec (encoder/decoder)stringent conditions on ﬂexible QoS requirements of WSN. which can process the information on various kinds of sensory The third sort of problems come from the constrained data. Also, Adaptive Coding Schemes which involve differentresources of WSN motes. A mote is battery powered, so has a codes are utilised to take advantage of the variations in channellimited power source. Also, computational power and memory conditions in wireless communications.space are limited in motes, and thus the algorithm to achieve 1 Microprocessors allow very easy and efﬁcient embedding of error controlreliability should not be computationally or storage intensive. in various layers of communication protocols where data is buffered
III. C ONTRIBUTION OF THE PAPER This paper proposes an Adaptive Universal FEC (AuFEC) scheme based on RS codec for reliability in WSN. Most of the RS codec implementations use Berlekamp-Massey (BM) algorithm  for locating the errors in the received data  . We show that Fitzpatrick (F) algorithm, along with an universal Galois Field (GF) Arithmetic Processor proposed Fig. 1. Diversiﬁed WSN features in N-to-1 Networking recently, is more suitable for WSN specially Type I and Type II systems. We employ a hardware/software codesign methodology for The above discussion is summarised in Table I for three efﬁcient implementation of the codec. The system is dy-discussed error control mechanisms for three type of systems namically partitioned based on the scheme being employed.in varying channel conditions. We present the two schemes and a Module for dynamic TABLE I partitioning in the system. Finally, we present the overheadsS CHEME S ELECTION FOR VARIOUS C HANNEL C ONDITIONS & S YSTEMS related with the uRS codec and implementation results on wireless motes. Scheme Zero Errors Low Error/Consistent High Error/Varying I √ II III I II III I II III IV. U NIVERSAL R EED S OLOMON A RCHITECTURE ARQ √ √ √ FEC √ √ √ √ √ Reed Solomon Decoder consists of four main blocks, GF AuFEC Arithmetic Processor, Syndrome Computation, Error Locator Computation and Error Location and Value Computation. All There are quite a few error correcting codes (ECC) that these blocks have to be studied with the notion of adaptabilityare useful in communication channels. Most prominent are and universality for designing an universal decoder. Universalthe BCH codes, linear block codes and Reed-Solomon (RS) Reed-Solomon (uRS) decoders allow ﬂexibility in some orcodes . RS codes are the most widely used codes because all of the code parameters: Information Length (k), Codewordof their simplicity and high performance  . Length (n), Error Correcting Capability (t), size of the Galois The rest of the paper is organised as follows. In Section Field (m) and Generator Polynomial (g). A single uRS decoderII, we brieﬂy review the work done related to this problem capable of decoding many different codes can be a moreand discuss the contributions of our paper in Section III. hardware-efﬁcient solution than separate decoders for each RSSection IV covers the Universal RS architectures suitable for code although it may be less hardware-efﬁcient than a RSWSN. We present a channel adaptation algorithm and related decoder that is optimised with respect to any individual codeconstraints in Section V and a System Design Perspective for or when the coding scheme is ﬁxed. Following subsectionsoptimum performance in Section VI. Performance Analysis discuss the architectures employed for design of uRS Codec.for the system is performed in Section VII and we concludethe paper with some ﬁnal remarks in Section VIII. A. Universal GF Arithmetic Processor II. R ELATED W ORK Research works on universal GF Arithmetic have mostly Energy-efﬁciency of FECs over various retransmission concentrated on GF multipliers neglecting inversion and divi-schemes for wireless communications has been studied in . sion. Most of the architectures presented to date use look-upFollowing the idea,   compare a few FEC schemes in tables for GF inversion. Due to memory constraints in WSN,WSN showing that ﬁxed & small ECC are not effective in it is not possible to store the inversion results for all the Galoisreducing packet losses when the errors are bursty. In a recent Fields (due to universality) which deﬁne the RS code. Somework , it has been shown that FEC schemes that are able to implementations also use External Memory/Arithmetic Unitcorrect short errors per codeword are not very useful and it is for the same purpose . However, this is also not suitablenecessary to implement efﬁcient RS codes in WSN depending for WSN due to higher access time and even higher poweron the applications. In , an open problem has been posed consumption due to data access and transfer.regarding achieving reliability in presence of different kinds of A GF Arithmetic processor was proposed in . Thissensory systems and varying channel conditions. In the ﬁeld processor can perform all the GF computations using the sameof FECs, Blahut  proposed the mathematical concept of architecture. This architecture suits best for Type I and Typeuniversal decoders. Building on these algorithms, Shayan et II systems for a simple reason that all GF computations canal. proposed  universal decoders that use a ﬁxed primitive be performed using a single block. A GF Multiplier will havepolynomial of a ﬁxed degree m, but can decode RS codes a better performance than multiplication using the processor.of different rates. An universal decoder based on Berlekamp Inversion and multiplication take the same number of cyclesMassey Algorithm is proposed in . Trade-offs related using the processor and hence, processor will have comparableto GF arithmetic on resource-sonstrained systems have been performance to any GF inverter because of high complexitystudied in great detail in . of GF inversion compared to multiplication.
B. Syndrome Computation V. C HANNEL A DAPTATION Syndrome computation depends on degree of Galois Field,generator polynomial and primitive polynomial. Calculation In many sensor network applications, the requirements areof generator polynomial requires intensive multiplication and not known precisely enough at deployment time to makesquaring of ﬁeld elements which is not suitable for our trade-offs required for maximum network utility. Even duringresource constrained systems. A low complexity architecture operation, requirements will change in response to varyingfor syndrome computation was proposed in  which erad- conditions. The challenge, then, lies in designing sensoricates the dependency of syndrome computation on generator network applications that can dynamically adapt to changingpolynomial. Our RS codec uses this architecture for comput- requirements by selecting different points in the design spaceing the syndromes. The primitive polynomial coefﬁcients are for trade-off resource consumption. In this section, we presenthardwired to the circuit. a platform independent adaptation algorithm for Adaptive Syndrome Computation block is the smallest in RS decoder RS Codecs, which which can be easily modelled for any(Figure 3, Hardware Size) and is the only block which does application communication scenarios.not depend on error rates. However, most of the power con-sumption comes from Syndrome Computation block (Figure 3, ————————————-Power Dissipation) because of large number of multiplications V ariables : i, j, noe, n;and high switching activity for every symbol it receives. Initialize : i = j = n = 0;C. Error Locator (1) : mm := Mn ; There are several algorithms developed for solving the (2) : tt := TMn , min;key equation. The most widely used algorithm for solving (3) : noe := [some integer];the key equation is BM algorithm . We compared the ∗ ∗number of errors f rom key solving ∗results of BM Algorithm with another algorithm developed (4) : if (noe < tt)by Fitzpatrick  known as F-algorithm. (5) : ACK & exit; (6) : elseif (j = 0) (7) : tt := tt + 1; (8) : if (tt = TM , max) (9) : j := 1; (10) : N ACK(tt, mm); (11) : endif ; (12) : elseif (i = 0) (13) : mm := Mn+1 ; (14) : tt := TMn+1 , min; (15) : n := n + 1; (16) : t := 0; Fig. 2. Software Timing Comparison of BM and F Algorithm (17) : if (Mn+1 = MM ax ) (18) : i = 1; Algorithm F for solving the key equation has the same com- (19) : N ACK(tt, mm);putational complexity as the BM algorithm. Both algorithms (20) : endif ;construct a sequence of pairs of polynomials with coefﬁcients (21) : elsein GF(2m ). F is controlled by two tests for zero, while BM (22) : N ACK(correction not possible);requires two tests for zero and an integer comparison test. (23) : exit;When µi = 0, one polynomial in F is multiplied by µi / µi . (24) : endif ;In this case, F-algorithm has half as many multiplications as in (25) : end;BM where one polynomial is multiplied by the discrepancy µ ————————————-and the other by 1/µ. This results in huge software instructionsaving and hence, time and software power which is shown The algorithm has two variables, mm and tt, which arein Figure 2. In terms of hardware, both the algorithms have degree of GF and error correcting capabilities of the system,similar sizes and power consumption, which are presented in respectively. The variables are assigned the values from aFigure 3. table provided by the user. There are two ﬂags i and j used Another reason for using F-algorithm in the universal de- in the algorithm which indicate the maximum degree of GFcoder for WSN is due to its construction which is very similar and maximum error correcting capability the system canto uGF Arithmetic Processor discussed earlier. The coefﬁcients operate on for corresponding degree of GF. Based on theof error locator polynomial are multiplied by µi / µi . This value of these ﬂags, values are chosen from the table. In casemakes the GF-processor and F-Algorithm more suitable for when the system is not able to correct the errors (noe > tt),resource-constrained WSN running on embedded processors. a N ACK is sent to the transmitter with changes in mm
Fig. 3. Hardware Comparison of BM and F Algorithm (a) Power Dissipation for zero error and 8 errors case and (b) Hardware sizeand tt decided by the algorithm. Once both the ﬂags have hardware-software co-design methodology with dynamic task-a value 1 indicating maximum error correction capability allocation (partitioning) for real time systems. To guide theof the system, a N ACK with correction not possible is partitioning process, design metrics are deﬁned to comparesent to the transmitter. The values in the table must obey the alternative partitioning and to evaluate their conformance withfollowing equation for avoiding redundant operations: respect to the system constraints. This section covers in detail a dynamic partitioning module for optimum performance of Mn ∗ TMn ,max < Mn+1 ∗ TMn+1 ,min (1) uRS Codec under some deﬁned Performance Metrics. TheIt is also important to ensure that the resources are not being ﬂow of our Dynamic Partitioning Module follows the one inwasted in processing while the errors can be corrected using , with major changes suitable for WSN. The overall systema smaller code. The following equation put another restriction architecture for our motes is presented in Figure 4.on values in the table: Mn ∗ (TMn ,max + 1) ≥ Mn+1 ∗ TMn+1 ,min (2)This is based on the fact that TMn ,max number of errorscorrected in GF(2Mn ) are less than TMn+1 ,min error correctionin GF(2Mn+1 ). Table II shows an example: TABLE II TABLE FOR VARIABLE A SSIGNMENT IN A DAPTATION A LGORITHM n Mn [TMn ,min , ...., TMn ,max ] Fig. 4. Wireless Mote System Architecture 0 4 [0, 1, ..., 4, 5] 1 8 [3, 4, 5] A. Performance Metrics 2 16 [3, 4, 5] 3 32 [3, 4] Partitioning plays an important role in ﬁnal system perfor- mance. Performance Metrics are deﬁned to guide the parti- tioning process based on the application of the system. The VI. S YSTEM L EVEL D ESIGN goal is to deﬁne a speciﬁc metrics to be applied at the system- level to measure and to compare the performance of several Most wireless sensor networks are composed of nodes design alternatives. These performance metrics are deﬁnedimplemented with embedded processors that execute software in terms of Hardware Execution time, Hardware Resourcebased instructions. These nodes are capable of functional requirements, Software Execution time, Memory Requirements,adaptation simply by loading and executing various software Power Speciﬁcation, etc. and can be any possible combinationprograms. However, this virtually unlimited ﬂexibility comes of these speciﬁcations. The idea of performance metrics forat a price, as software algorithms executed on processors power aware systems is discussed in .typically consume more energy and have lower performancethan Application Speciﬁc Integrated Circuit (ASIC) or FPGA B. Dynamic Partitioning Modulebased implementations. However, ﬁxed-logic implementation Our dynamic partitioning was employed using two schemes.do not have the ﬂexibility to reap the beneﬁts provided by dy- We discuss the various blocks in the dynamic partitioningnamic adaptability. Because of this efﬁciency/ﬂexibility trade- module for better understanding of the two schemes beforeoff inherent in node design, a wide range of implementation discussing the schemes. The block diagram for dynamic parti-options are worth consideration. Flexibility being expensive, tioning module is shown in Figure 5. The module is composedﬁnding the implementation that satisﬁes the ﬂexibility needs of three main blocks, CoRe Block, ParES Block and AASof an application will ensure highest efﬁciency. This requires a Block.
Fig. 5. Dynamic Partitioning Module and ParES Block for (a)Scheme A (b)Scheme B CoRe Block: This is the Constraints and Recommendation Scheme B: This scheme is a simpler version of SchemeBlock. It receives the parameters from the Set Parameter Block A and is more suitable for resource constraint systems. Theand recommends the ParES block an initial conﬁguration for scheme incorporates a look-up table with related system costsdynamic partitioning. This recommendation may be based for all the possible task assignments. The system, whenon the initial constraints provided by the user or system provided with the constraints, simply uses the look-up table toconstraints. These constraints can also include classiﬁcation of ﬁnd the solution for the given cost functions. Implementationtasks which are more suitable to be implemented on Hardware. of Scheme B gives a much faster dynamic partitioning solution ParES Block: This is the Partitioning, Evaluation and but is platform dependent as the partitioning results of SchemeStrategy Block. It receives the initial recommendation from the A are precomputed and stored as look-up tables.CoRe block and calculates the cost function for this partition- Scheme Selection: Scheme B is basically a simpliﬁed anding scheme in Evaluation Subblock. Now the problem amounts precomputed version of Scheme A. While Scheme A is prefer-to a Decision Problem which has a lower time complexity than able if the implementation is expected to migrate over variousOptimization Problem. If initial recommendation doesn’t have systems, Scheme B is more suitable for further reducing thea possible solution, a new strategy is chosen in the Strategy processing. With the increase in design space options, size ofsubblock and evaluation is done for the cost value. Finally, the Scheme A increases exponentially and so does the processing.partitioning scheme with the lowest cost function is declared For designs with large number of implementation options andand notiﬁed to the AAS Block. ﬁxed platform, Scheme B is more preferable. AAS Block: This is the Allocation, Assignment and Schedul-ing Block. It associates the tasks with Hardware and Software VII. P ERFORMANCE A NALYSISand maintains the scheduling of the tasks during the execution In this section, we discuss the platform for our implemen-of the program. This block also controls the interface between tation and present some results for universal Reed Solomonthe hardware and microprocessor by maintaining control sig- decoder.nals during execution of the program. A. Platform DescriptionC. Dynamic Partitioning Schemes We use as the underlying platform wireless motes , Two Dynamic Partitioning schemes can be used in ParES which has an FPGA submodule, a wireless transceiver sub-Block. Scheme A is based on computational model and module, a sensor submodule and a coin cell battery submodule.provides a general partitioning scheme for any Hardware- The hardware part of the system is mapped on the FPGASoftware Partitioning System. It relies on an execution ﬂow submodule which uses a Xilinx Spartan IIE device. The micro-graph and computes the partitioning cost. The complexity of controller is the Atmel Atmega 128L 8-bit RISC architecturethis scheme increases exponentially with the number of tasks with 128 kb in-system programmable ﬂash memory. Thein the system. Scheme B relies on a look-up table which software part of our system is mapped on this submodule.contains the cost value for any speciﬁed partitioning scheme. The transceiver submodule consists of a Nordic nRF2401 2.4This cost value is calculated in Scheme A by traversing GHz ISM band RF transceiver.through the execution ﬂow graph. Scheme A: The system speciﬁcations are provided to the B. Implementation Resultspartitioning module in the form of an execution ﬂow graph. All the experiments were performed on the wireless motesThis is a directed ﬂow graph representing the trace and developed by Tyndall National Institute  and the softwareexecution order of various blocks in the uRS architecture. The timing analysis was done on 2.6 GHz Pentium 4 processor.nodes of this graph represent the tasks to be performed and the Table III presents the results for a GF(28 ) 4-error correctingedges represent the value of the performance metrics for that universal decoder. The running system in best case takestask. The task is then, to ﬁnd the minimum distance between approximately 136000 clock cycles. Measured power for thethe source and sink node while satisfying the total hardware universal decoder for GF(216 ) amounted to 957 mW and thatarea and memory requirements. for GF(24 ) amounted to 213 mW.
TABLE III R ESULTS FOR U NIVERSAL R EED S OLOMON I MPLEMENTATION Hardware Software RS Decoder Blocks Slices Gate Speed Flash SRAM Speed Equivalent (MHz) (Bytes) (Bytes) (#Cycles) Syndrome Computation 23 440 359.7 1060 76 8000 Galois Field Processor 350 5979 74.2 1368 21 223 F-algorithm & Error Evaluation 352 6128 43.5 2790 276 125000C. System Overhead R EFERENCES While the savings obtained by adapting to the channel  C. Wang, K. Sohraby, B. Li, M. Daneshmand and Y. Hu: A Survey ofconditions are signiﬁcant, we must ensure that the cost of Transport Protocols for Wireless Sensor Networks, Network, IEEE, 2006, 20(3): pp. 34-40run-time adaptation does not overweigh the beneﬁts of recon-  R. Blahut: Theory and Practice of Error-Control Codes, Addison-Wesley,ﬁguration. To measure the cost of run-time adaptation and Readings, MA, 1983reconﬁguration costs, we ﬁrst present the costs of selecting  R. Agarwal, E. M. Popovici, C. O’Keeffe, B. O’Flynn and S. J. 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