History of CPU Architecture


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Presentation for a lecture in the doctoral series at Stefan cel Mare University, Suceava, Romania, May 2009.
Aim was to show current generation the rich history of computer hardarware and that many of the recent innovations in CPU design have their origins in designs of teh 50s and 60s.

Published in: Technology, Education

History of CPU Architecture

  1. 1. CPU Architecture Historical Perspective Leading to the CPU of today’s PCs OLLSCOIL LUIMNIGH UNIVERSITY OF LIMERICK Timothy Hall Dept Electronic & Computer Engineering, University of Limerick Professor (hc) Computer Science, Stefan cel Mare University of Suceava
  2. 2. CPU Architecture <ul><li>What questions am I trying to answer? </li></ul><ul><ul><li>Why is the architecture of the CPU of a PC the way it is? </li></ul></ul><ul><ul><li>What influences of theory, engineering and commerce were there in its evolution? </li></ul></ul><ul><ul><li>What is the relationship between system and CPU architecture? </li></ul></ul>
  3. 3. CPU Architecture <ul><li>Why me? </li></ul><ul><ul><li>Born in the year the transistor was invented </li></ul></ul><ul><ul><li>Studied Semiconductor Physics, digital systems and Communications theory </li></ul></ul><ul><ul><li>Worked in the computer industry as a hardware engineer during the introduction of the VDU and remote access </li></ul></ul><ul><ul><li>Designed mini- and micro-computer driven test equipment at the birth of the microprocessor era </li></ul></ul><ul><ul><li>Taught microprocessor engineering since the early 1980s </li></ul></ul><ul><ul><li>Teach advanced topics in CPU design to Masters students </li></ul></ul>
  4. 4. CPU Architecture &quot;I think that there is a world market for maybe five computers.&quot; 
 - remark attributed to Thomas J. Watson, chairman of IBM, 1943
  5. 5. CPU Architecture <ul><li>There are four factors influencing CPU evolution: </li></ul><ul><ul><li>Technology (constraint or opportunity) </li></ul></ul><ul><ul><li>Theory and design inginuity </li></ul></ul><ul><ul><li>User demand </li></ul></ul><ul><ul><li>Economics & commercial pressure </li></ul></ul>
  6. 6. Technology Relays, Thermionic valve, Diodes and Bipolar Transistors, RTL then TTL integrated circuits, MOS integrated circuits, LSI and VLSI
  7. 7. Theory and design ingenuity
  8. 8. User Demand
  9. 9. Economics & Commercial Pressure
  10. 10. CPU Architecture Where to start? Not here! www.computersciencelab.com/ComputerHistory/History.htm
  11. 11. CPU Architecture <ul><li>Where to start? </li></ul><ul><li>1930/40s </li></ul><ul><li>Why? </li></ul><ul><ul><li>Concepts: digital, electronic, demand </li></ul></ul><ul><ul><li>Theory: Turing, Shannon, von Neumann </li></ul></ul><ul><ul><li>Pioneers: Zuse (Z3), Stibitz (model K), Newman, Flowers & Combs (Colossus), Turing, von Neumann, Eckert & Mauchley (ENIAC) </li></ul></ul>
  12. 12. CPU Architecture <ul><li>In the decade 1943 (ENIAC) to 1953 (IBM 701) theory, engineering design, technological inginuity flourished. </li></ul><ul><li>The 2 nd World War brought together key actors and lent an urgency to their work, this was followed by a commercial race to bring the new developments to the market </li></ul><ul><li>The decade ends just as the first Si transistor designs and magnetic core memory were introduced. </li></ul><ul><li>Here are some key developments: </li></ul>
  13. 13. CPU Architecture Eckert & Mauchley ENIAC: Begun 1943 finished 1946 5000 operations a second Programmed by plugboard & switches I/O: card, lights, plugs, switches Size: floor area 100 sq metres
  14. 14. CPU Architecture Colossus 1. 1944 Used for code breaking by the British Programmed by Patch cord and switches I/O: paper tape, teleprinter 1500 thermionic valves 5000 operations a second Reliability?: Never switched off unless malfunctioned. Followed by Colossus Mk2, 2400 valves, 25000 operations a second
  15. 15. CPU Architecture Harvard Mark 1 1944: Electromechanical, programmable (really an automatic calculator),16m long, 2m high, more reliable than contempary valve machines
  16. 16. CPU Architecture EDSAC. 1949 First practical programmable stored program computer 1k words of memory 17 bit word Mercury delay line memory 700 operations a second I/O: punched tape, teleprinter Programmed by a primitive assembler set-up by hand on uniselectors and transferred into memory. Wilkes: Cambridge University Mathematics Lab
  17. 17. CPU Architecture <ul><li>&quot;Computers in the future may weigh no more than 1.5 tons.&quot; -Popular Mechanics, 1949 </li></ul>b
  18. 18. CPU Architecture “ From then on, when anything went wrong with a computer, we said it had bugs in it (an error in the 1940s Harvard mark 11 computer was traced to a moth trapped inside).” - Rear Admiral Grace Murray Hopper, US Navy
  19. 19. CPU Architecture Manchester Mark 1 . 1949 Begun 1947 1300 valves Memory: 128 + 1024 40 bit words Memory: Cathode Ray tube and magnetic drum I/O: papertape, teleprinter Programming: switches Add time 1.8 microseconds Design: Williams & Kilburn
  20. 20. CPU Architecture <ul><li>Early Memory Technology </li></ul><ul><li>Mercury ( acoustic) Delay Line </li></ul><ul><li>Cathode Ray Tube (Williams tube) </li></ul><ul><li>Magnetic Drum </li></ul>1 2 3
  21. 21. CPU Architecture <ul><li>All these memory devices operate as a long shift register. No random access. </li></ul>Data enters, takes some time to travel to the output and is recirculated. Data can only be read as it reaches the output – there is a waiting time, latency, for it to appear. Storage is achieved by this I/O delay and recirculation. Mercury delay line – acoustic delay. Williams tube – phosphor persistence. Magnetic drum – diameter and speed. Data in mercury delay line and cathode ray tube is volatile, if not recirculated it is lost. Magnetic drum is non-volatile.
  22. 22. CPU Architecture SEAC 1950 Diode logic 10500 diodes and 1500 valves Mercury delayline memory 512 words 45 bits Clock 1MHz Add 864 microseconds Magnetic Tape external storage I/O: teleprinter or mag tape & remote teleprinter Used for scientific calculation: Meteorology, navigation etc..
  23. 23. CPU Architecture ACE 1950 Start of project:1948 Completed:1950 Add time:1.8 microseconds Input/output:cards Memory size:352 32-digit words Memory type:delay lines Technology:800 valves Floor space:1.5 sq metres Project leader:J. H. Wilkinson
  24. 24. CPU Architecture <ul><li>1951 First Commercial Computers: </li></ul><ul><li>LEO (Lyons Electronic Office). Designed for production scheduling for Lyon’s Tea Shops, UK </li></ul><ul><li>UNIVAC 1. Made by Remington Rand for US Census Office </li></ul>
  25. 25. CPU Architecture <ul><li>Speed:1,905 operations per second </li></ul><ul><li>Input/output:magnetic tape, unityper, printer </li></ul><ul><li>Memory size:1,000 12-digit words </li></ul><ul><li>Memory type:delay lines, magnetic tape </li></ul><ul><li>Technology:valves </li></ul><ul><li>Floor space:11 sq metres </li></ul><ul><li>Cost: approx $1million </li></ul><ul><li>Project leaders:Eckert and Mauchley </li></ul>UNIVAC 1. 1951
  26. 26. CPU Architecture Clock 500kHz Instruction time 1.5 ms Multiple I/O streams I/O: paper tape & punch, card reader & punch, mag tape Memory: mercury delay line 2048 35 bit words Initially used for production planning, later for inventory and payroll – 1 st MIS LEO 1951
  27. 27. CPU Architecture IBM 701. 1953 IBM’s first commercial scientific computer. 19 were sold. KOMPILER compiler and run-time environment, later FORTRAN Memory 2048 36 bit words (expandable to 4096) Multiply/divide 456 microseconds
  28. 28. CPU Architecture Magnetic Core Memory. First used in Whilrwind computer 1953 First Random Access memory. Non-volatile. Faster and more reliable than earlier memory technology
  29. 29. CPU Architecture Memory access is as a read/write cycle Required address is decoded as X & Y coordinates and a current pulse applied If the core where X & Y are coincident is a 0 no signal on the sense line, if a 1 the magnetic state of the core is flipped and there is a sense pulse This read is destructive so the data has to be written back Magnetic core memory is non-volatile Magnetic Core Memory
  30. 30. CPU Architecture 1954. Silicon Transistor Texas Instruments 1955. TRADIC Bell Labs First transistorized computer 800 transistors 10000 diodes Power less than 100 Watts (a twelfth power required by valves) In the photo a program is being Loaded via a plugboard
  31. 31. CPU Architecture <ul><li>These machines, though of varying architecture and capability, have features that have been absorbed and re-used in the computers that followed. There are very few ideas or features that have been introduced since that are not echoes of what went before. </li></ul>
  32. 32. CPU Architecture <ul><li>The next era is that of the Mainframe. </li></ul><ul><li>Bigger, more powerful, and expensive. </li></ul><ul><li>Two main applications: business </li></ul><ul><li>applications, accounting, MIS….. </li></ul><ul><li>and scientific applications requiring vast </li></ul><ul><li>numbers of simple calculations….. </li></ul><ul><li>And later the Minicomputer was developed </li></ul>
  33. 33. CPU Architecture IBM´s 7000 series mainframes were the company's first transistorized computers. Top of the line was the 7030 &quot;Stretch.&quot; Nine of the computers, which featured a 64-bit word and other innovations, were sold to US national laboratories and other scientific users. It’s designer L. R. Johnson first used the term &quot;architecture&quot; in describing the Stretch. 1959 IBM 7000 series
  34. 34. CPU Architecture 1960 DEC PDP1 50 were build, cost $120,000. It had a cathode ray tube graphic display, needed no air conditioning and required only one operator. The display intrigued early hackers at MIT, who wrote the first computerized video game, SpaceWar!, for it. SpaceWar became The standard demonstration on all 50.
  35. 35. CPU Architecture Fairchild invented the resistor-transistor logic (RTL). The first product a set/reset flip-flop and the first integrated circuit available as a monolithic chip. 1961 RTL ICs
  36. 36. &quot; But what...is it good for?&quot; 
 -Engineer at the Advanced Computing Systems Division of IBM, 1968, commenting on the microchip
  37. 37. CPU Architecture <ul><li>1963 to 1966 TTL </li></ul><ul><li>Transistor Transistor Logic. </li></ul><ul><li>First introduced by Sylvania for US military </li></ul><ul><li>Commercial devices by Texas Instruments 7400 family. </li></ul>
  38. 38. CPU Architecture 1964 IBM System/360 IBM System/360: a family of six mutually compatible computers and 40 peripherals that could work together. The initial investment of $5 billion was quickly returned as orders for the system climbed to 1,000 per month within two years. At the time IBM released the System/360, the company was making a transition from discrete transistors to integrated circuits, and its major source of revenue moved from punched-card equipment to electronic computer systems.
  39. 39. CPU Architecture Digital Equipment Corp. introduced the PDP-8, the first commercially successful minicomputer. The PDP-8 sold for $18,000, one-fifth the price of a small IBM 360 mainframe. The speed, small size, and reasonable cost enabled the PDP-8 to go into thousands of manufacturing plants, small businesses, and scientific laboratories. 1965 DEC PDP8
  40. 40. CPU Architecture <ul><li>Virtually all these machines have recognizable architecture based Turing Machine and von Neumann architecture. </li></ul><ul><li>Here’s an examples that differ and points to modern Supercomputers. </li></ul>
  41. 41. CPU Architecture CDC´s 6600 supercomputer, designed by Seymour Cray, performed up to 3 million instructions per second. The 6600 retained the distinction of being the fastest computer in the world until surpassed by its successor, the CDC 7600, in 1968. Part of the speed came from the computer's design, which had 10 small computers, known as peripheral processors, funneling data to a large central processing unit. 1964 CDC 6600
  42. 42. CPU Architecture Hewlett-Packard entered the general purpose computer business with its HP-2115, offering a computational power formerly found only in much larger computers. It supported a wide variety of languages, among them BASIC, ALGOL, and FORTRAN. The photo shows the familiar teleprinter for papertape I/O and printer for output. The CPU with binary display and switches. Thes second box is core memory 1966 HP-2115
  43. 43. CPU Architecture Fairchild produced the first standard metal oxide semiconductor MOS product for data processing applications, an eight-bit arithmetic unit and accumulator. 1967 1 st data processing MOS ic
  44. 44. CPU Architecture Data General Corp., started by a group of engineers that had left DEC., introduced the Nova, with 32 kilobytes of memory, for $8,000. In the photograph, Ed deCastro, president and founder of Data General, sits with a Nova minicomputer. The simple architecture of the Nova instruction set inspired Steve Wozniak´s Apple I board eight years later. 1968 DG Nova
  45. 45. CPU Architecture <ul><li>This brings us to the dawn of the Microprocessor era – a convenient point to discuss the underlying theory: </li></ul><ul><li>Binary data </li></ul><ul><li>Turing Machine </li></ul><ul><li>Von Neumann architecture </li></ul><ul><li>Basic CPU architecture </li></ul>
  46. 46. CPU Architecture <ul><li>Binary Data </li></ul><ul><li>Data and other information is stored and processed by electronic circuits that have only two states (0/1:Lo/Hi:OFF/ON). Bits. </li></ul><ul><li>Several bits together represent the data according to standard coding systems. Words. </li></ul><ul><li>01100001=a in ASCII </li></ul>
  47. 47. CPU Architecture A thought experiment by the English Mathemetician Alan Turing in 1936. Decisions are based on the current state (the result of what happened before) and the data being read, the “head” moves back and forth based on this decision. This encapsulates the action of a digital computer’s CPU, the current state and new data are manipulated according to an instruction and what happens next is determined.
  48. 48. CPU Architecture Von Neumann architecture. Data and instructions are stored in memory, the Control Unit takes instructions and controls data manipulation in the Arithmetic Logic Unit. Input/Output is needed to make the machine a practicality Memory Control ALU I/O
  49. 49. CPU Architecture CPU Architecture The ALU manipulates two binary words according to the instruction decoded in the Control unit. The result is in the Accumulator and may be moved into Memory.
  50. 50. CPU Architecture <ul><li>von Neumann architecture introduces a problem, which is not solved until much later. </li></ul><ul><li>The CPU work on only one instruction at a time, each must be fetched from memory then executed. During fetch the CPU is idle, this is a waste of time. Made worse by slow memory technology compared with CPU. </li></ul><ul><li>Time is also lost in the CPU during instruction decode. </li></ul>F E F E --------- D E
  51. 51. CPU Architecture <ul><li>Take a closer look at the action part of the CPU, the ALU, and how data circulates around it. </li></ul><ul><li>An ALU is combinational logic only, no data is stored, i.e. no registers. This is the original reason for having CPU registers. </li></ul><ul><li>By convention the output of a CPU is stored in the Accumulator ¹ , but what about the inputs? </li></ul><ul><li>¹ Accumulator because original ALUs worked one bit at a time and “accumulated” the answer </li></ul>
  52. 52. CPU Architecture CPU Architecture ALU A X Y In the simplest, minimum hardware, solution one of them, say X, is the accumulator A, the other, Y, is straight off the memory bus (this requires a temporary register not visible to the programmer). The instruction may be ADDA, which means: add to the contents of A the number (Y) and put the answer in A. data bus
  53. 53. CPU Architecture <ul><li>It’s a simple step to add more CPU data registers and extend the instructions to include B, C,….. as well as A. </li></ul><ul><li>An internal CPU bus structure then becomes a necessity, but how many busses? Designs exist with 1,2, or 3. </li></ul><ul><li>(Look up the details if you’re interested.) </li></ul>
  54. 54. CPU Architecture
  55. 55. CPU Architecture <ul><li>Bus A delivers data to </li></ul><ul><li>one input of the ALU </li></ul><ul><li>bus B the other, the </li></ul><ul><li>convention of the ALU </li></ul><ul><li>output going to A </li></ul><ul><li>usually holds. </li></ul><ul><li>Connections to the data bus </li></ul><ul><li>not shown. You can work </li></ul><ul><li>out how a 1 or 3 bus system </li></ul><ul><li>would work. </li></ul>A B N ALU bus A bus B
  56. 56. CPU Architecture <ul><li>1970?: Semiconductor Memory </li></ul><ul><li>The technology that enabled the </li></ul><ul><li>production of microprocessors </li></ul><ul><li>developed out of the rise of </li></ul><ul><li>semiconductor memory, first static </li></ul><ul><li>and later dynamic RAM. </li></ul><ul><li>The random access of core memory </li></ul><ul><li>but occupying much smaller space </li></ul><ul><li>and costing much less. </li></ul><ul><li>Uses MOS technology, data is stored </li></ul><ul><li>on a MOS capacitor (dynamic) or in a </li></ul><ul><li>F/F (static). </li></ul><ul><li>The development of the semiconductor </li></ul><ul><li>industry becomes dependant on </li></ul><ul><li>memory technology, Moore’s Law. </li></ul>
  57. 57. CPU Architecture <ul><li>We’ve reached the point at which the first microprocessors appear: 1971 INTEL 4004 </li></ul>The first advertisement for a microprocessor, the Intel 4004, appeared in Electronic News. Developed for Busicom, a Japanese calculator maker, the 4004 had 2250 transistors and could perform up to 90,000 operations per second in four-bit chunks. Federico Faggin led the design and Ted Hoff led the architecture. INTEL realized they had a good idea and extended it to a general purpose device…..
  58. 58. CPU Architecture 1972: INTEL 8008 A vast improvement over the 4004, its eight-bit word afforded 256 unique arrangements of ones and zeros. For the first time, a microprocessor could handle both uppercase and lowercase letters, all 10 numerals, punctuation marks, and a host of other symbols, as in ASCII. And led to the early microcomputers….
  59. 59. CPU Architecture 1973: Micral The Micral was the earliest commercial, non-kit personal computer based on a micro-processor, the Intel 8008. Thi Truong developed the computer and Philippe Kahn the software. Truong, founder and president of the French company R2E, created the Micral as a replacement for minicomputers in situations that didn´t require high performance. Selling for $1,750, the Micral never penetrated the U.S. market. In 1979, Truong sold Micral to Bull. There are other very early microcomputers, see: www.digibarn.com/stories/bill-pentz-story/index.html The 8008 was quickly followed by the more functional 8080….
  60. 60. CPU Architecture 1975: Altair 8800 The January edition of Popular Electronics featured the Altair 8800 computer kit, based on Intel 8080 microprocessor, on its cover. Within weeks of the computer's debut, customers inundated the manufacturing company, MITS, with orders. Bill Gates and Paul Allen licensed BASIC as the software language for the Altair. Ed Roberts invented the 8800 — which sold for $297, or $395 with a case — and coined the term &quot;personal computer.&quot; The machine came with 256 bytes of memory (expandable to 64K) and an open 100-line bus structure that evolved into the S-100 standard.
  61. 61. CPU Architecture 1976: Apple 1 Steve Wozniak designed the Apple I, a single-board computer. With an order for 100 machines at $500 each from the Byte Shop, he and Steve Jobs got their start in business. In this photograph of the Apple I board, the upper two rows are a video terminal and the lower two rows are the computer. The 6502 microprocessor in the white package sits on the lower left. About 200 of the machines sold before the Apple 2 was introduced.
  62. 62. CPU Architecture 1976 also saw the introduction a famous supercomputer the Cray 1. It made its name as the first commercially successful vector processor. The fastest machine of its day, its speed came partly from its shape, a C, which reduced the length of wires and thus the time signals needed to travel across them. The electronics generated a lot of heat needing liquid cooling the mechanism for forms the seating around the base. Project started:1972 completed:1976 Speed:166 million floating-point operations per second Size:58 cubic feet Weight:5,300 lbs. Technology: Integrated circuit ECL Clock rate:83 MHz Word length:64-bits Instruction set:128 instructions 1976 Cray 1
  63. 63. CPU Architecture more info: http://www.z80.info/zip/z80pps.zip The Zilog Z-80 could run any program written for the 8080. It had many features that made it useful in microcomputers to run HLLs, many extra instructions and two sets of CPU registers. 1976 Zilog Z80
  64. 64. CPU Architecture The Commodore PET (Personal Electronic Transactor) — the first of several personal computers released in 1977 — came fully assembled and was straightforward to operate, with either 4 or 8 kilobytes of memory, two built-in cassette drives, and a membrane &quot;chiclet&quot; keyboard . The Apple II became an instant success when released in 1977 with its printed circuit motherboard, switching power supply, keyboard, case assembly, manual, game paddles, A/C powercord, and cassette tape with the computer game &quot;Breakout.&quot; When hooked up to a color television set, the Apple II produced brilliant color graphics. 1977 Commodore PET, APPLE II
  65. 65. CPU Architecture 1978: DEC VAX 11/780 The VAX 11/780 from DEC featured the ability to address up to 4.3 gigabytes of virtual memory, providing hundreds of times the capacity of most minicomputers, But essentially marks the end of the Minicomputer era.
  66. 66. CPU Architecture <ul><li>8 bit Microprocessors: Middle 1970s. </li></ul><ul><li>Intel 8080, Motorola 6800, MOSTec 6502, Zilog Z80. </li></ul><ul><li>40 pin DIL package, 8 bit word, 16 bit </li></ul><ul><li>Address, inexpensive. </li></ul><ul><li>Up to 256 Instruction (usually much less) </li></ul><ul><li>64k memory address space. Memory mixture of ROM (non-volatile: bios, loader) and RAM (volatile: programs and data). </li></ul><ul><li>I/O buffered connection to outside world </li></ul><ul><li>About 30,000 transistors </li></ul>
  67. 67. CPU Architecture Address Bus 16 bits Data Bus 8 bits Control signals System Architecture 8bit Micro
  68. 68. CPU Architecture <ul><li>Typical CPU Registers </li></ul><ul><li>A- Accumulator </li></ul><ul><li>B- GP data register </li></ul><ul><li>IX- Index register </li></ul><ul><li>ADDs- 16 bit Address </li></ul><ul><li>S- Stack Pointer </li></ul><ul><li>CC- Condition Codes </li></ul>A B IX ADDs S CC
  69. 69. CPU Architecture <ul><li>Typical Instruction Set </li></ul><ul><li>Data : arithmetic and logical manipulation of data. Result into A or sets CCs </li></ul><ul><li>Load/Store : Move data/addresses in and out of registers </li></ul><ul><li>Program : branch, jump, push, pull, interrupt, return, NOOP </li></ul>
  70. 70. CPU Architecture <ul><li>Typical Addressing Modes: Where is the data? </li></ul><ul><li>Direct : in register </li></ul><ul><li>Immediate : in the program </li></ul><ul><li>Implied : the instruction tells e.g DECA </li></ul><ul><li>Absolute/Zero page : at the address (16 or 8 bit) </li></ul><ul><li>Relative : offset from where you are now </li></ul><ul><li>Indexed : at address incremented content of index reg </li></ul><ul><li>and often combinations of the above </li></ul>
  71. 71. CPU Architecture <ul><li>Though these 8 bit micros led to the development of the general purpose personal computer the limited number of CPU registers, limited address space and simple addressing modes led to problems. </li></ul><ul><li>How do you enable users to program in an HLL when you need an operating system and maybe a BIOS underneath without constantly swapping register content in and out of memory? </li></ul><ul><li>(The Z80 partially solved this by having two sets of CPU registers, other solutions relied on compiling HLL into machine code as early mainframes had done.) </li></ul>
  72. 72. CPU Architecture The Motorola 68000 microprocessor exhibited a processing speed far greater than its contemporaries. This high performance processor found its place in powerful work stations intended for graphics-intensive programs common in engineering. 1979: 16 bit Microprocessors 16 bit micros were designed for use in microcomputer. More general purpose registers, bigger address space, more possible levels of indirection in addressing to allow virtual addresses. About 200,000 transistors
  73. 73. CPU Architecture Another requirement of HLLs was the ability to carry out floating point maths, programming the algorithms was tedious and execution slow – hence the idea of a co-processor with hardware for FP maths. This is the INTEL 8087 introduced in 1980 Maths co-processor for the 8088. The maths processor eventually become part of the CPU.
  74. 74. CPU Architecture 1981: The IBM PC IBM introduced its PC, igniting a fast growth of the personal computer market. The first PC ran on a 4.77 MHz Intel 8088 microprocessor and used Microsoft´s MS-DOS operating system.
  75. 75. CPU Architecture 640K ought to be enough for anybody. -Bill Gates, Microsoft 1981
  76. 76. CPU Architecture <ul><li>1982: 8052 Microcontroller </li></ul><ul><li>Enough transistors could be crammed onto a chip at this time to get all of an 8 bit system, CPU, memory and I/O on a single chip leading to microcontrollers and eventually embedded systems. </li></ul>
  77. 77. CPU Architecture 1987 INTEL 386: IBM PS/2 Intel 386 32 bit architecture. IBM Personal System/2, with an Intel 80386 CPU, 2 megabytes of memory, 3 ½ inch floppy a nd a 40 megabyte hard drive.
  78. 78. CPU Architecture <ul><li>Back to the deficiencies of system and CPU architecture. </li></ul><ul><li>The memory gap – as memory address space gets bigger and virtual memory becomes common the place where the data is stored could be very remote from the CPU in slow static memory or even on a disk, the time taken to retrieve it is a serious problem. </li></ul><ul><li>The solution Cache memory , include on the CPU chip (L1) or close by (L2) some local fast memory. Experience shows that the most frequently needed data is close to the current data so whilst the CPU is busy executing instructions pull into Cache the data/instructions around the current place. In most cases the next data/instruction will then be in Cache. </li></ul>
  79. 79. CPU Architecture <ul><li>Pre-fetch and Pipeline </li></ul><ul><li>During the execute part of the CPU cycle the instruction decode logic isn’t doing anything, it could be decoding the next instruction. Again, the next instruction is most likely the next one in the program so fetch it and begin to decode it whilst the current instruction is executing. The execution unit (ALU, registers etc..) can thus be kept going at full speed. </li></ul>
  80. 80. CPU Architecture Pre-fetch and Pipeline cont. Pipeline increases latency – it takes multiple clock cycles to from entering the pipeline to execution. When the next instruction is not the next in the pipe everything has to be thrown out. These two problems limit the practical length of a pipeline. Separate instruction and data caches are common.
  81. 81. CPU Architecture <ul><li>As VLSI technology advances the size of individual transistors reduces, more an a chip but also the operate faster. CPU for PCs become more and more powerful. </li></ul><ul><li>Co-processors, cache, pipeline, 32/64 bit word as illustrated by the INTEL family from 386 to Intanium II. </li></ul><ul><li>1985 275,000 </li></ul><ul><li>Pentium 1993 3,100,000 </li></ul><ul><li>Pentium 4 2000 42,000,000 </li></ul><ul><li>Itanium 2 2004 592,000,000 </li></ul><ul><li>The needs of most users and applications are being met but there are problems in the hardware. </li></ul>
  82. 82. CPU Architecture 1987: Motorola 68030 32-bit enhanced microprocessor with a central processing unit core, a data cache, an instruction cache, an enhanced bus controller, and a memory management unit in a single VLSI device — all operating at speeds of at least 20 MHz.
  83. 83. CPU Architecture 1993: INTEL Pentium
  84. 84. CPU Architecture <ul><li>Hardware problems of today's CPU chips. </li></ul><ul><li>1. Heat dissipation : small size, millions of transistors, how to extract the heat? Modern packaging. Also, reduce the heat by lowering the power supply voltage (5v to 3.3v ….) there is a limit, signals also get smaller the noise does not. </li></ul>
  85. 85. CPU Architecture <ul><li>Hardware problems of today's CPU chips. </li></ul><ul><li>2. Clock Distribution : As the number of transistors goes up it become more difficult to distribute clock signals to synchronize everything. Clock distribution circuitry become an unacceptable overhead. The solution? Dual and Quad core (Quad core Itanium Tukwila, 2008, 2,000,000,000). The parallel processing that this enables again has limits of usefulness as it has a programming overhead. </li></ul>
  86. 86. CPU Architecture <ul><li>This brings us up to date. </li></ul><ul><li>What have I left out? RISC architecture, modern embedded systems processors, DSP, Graphic processors… The structure and features of these echo the main-stream PC CPU. </li></ul><ul><li>What of the future? I won’t predict, but eventually we will have a shift in technology and the CPU will be organic. </li></ul>
  87. 87. CPU Architecture <ul><li>Any teacher that can be replaced by a computer, deserves to be.” - David Thornburg (American educationalist) </li></ul>
  88. 88. CPU Architecture? “ The best computer is a man, and it's the only one that can be mass-produced by unskilled labour” - Wernher von Braun
  89. 89. CPU Architecture <ul><li>References </li></ul><ul><li>1. Siewiorek, Bell & Newell: Computer Architecture . McGraw Hill 1980 </li></ul><ul><li>The best reference book to early hardware, long out of print. </li></ul><ul><li>2. http ://www.computerhistory.org/timeline/ a very detailed walk through history </li></ul><ul><li>3. Wikipedia (provided you confirm the information with anther source) </li></ul><ul><li>4. CPU manufacturers data and application information INTEL, AMD, Motorola </li></ul><ul><li>5. Many excellent text on specific CPUs particularly the 16 and 32 bit ones </li></ul><ul><li>6. Computer Architecture : A Quantitative Approach by David A. Patterson, John L. Hennessy, 4th Edition Morgan Kaufman Publishers 2007. The best advanced book on Computer Architecture. </li></ul><ul><li>7. The work of Masters students of my course CPU Architecture shared at: http://moodle.emrc.ul.ie . login as guest navigate Science & Engineering/Electronics & Computer Engineering/EE6442S09. </li></ul>