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Term paper of cse(211) avdhesh sharma c1801 a24 regd 10802037


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Term paper of cse(211) avdhesh sharma c1801 a24 regd 10802037

  1. 1. Term paper ooff ccoommppuutteerr oorrggaanniizzaattiioonn aanndd aarrcchhiitteeccttuurree ((221111)) Topic Shared Memory MIMD Architecture SUBMITTED TO SUBMITTED BY Miss Kamalpreet kaur NAME Avdhesh sharma COURSE B.Tech (cse) 150 REGG. NO. 10802037 ROLL NO. A 24 SEC c1801
  2. 2. ACKNOWLEDGEMENT History of all great works into witness that no great work was ever done without either active or passive support of a person ‘surrounding and one’s close quarters. thus is it not hard to conclude how active assistance from senior could positively impact the execution of a project .I am highly thankful to our learned faculty Miss Kamalpreet Kaur for his active guidance throughout the completion of project . Last but not least, I would also want to extend my appreciation to those who could not be mentioned here but have well played their role to inspire me behind the certain. AVDHESH SHARMA Contents
  3. 3. 1>>Introduction to MIMD Architectures 2>>MIMD Architecture’s Goal 3>>Routing 4>>The types of deterministic routing 5>>Shared memory :bus based 6>>Shared Memory: Extended 7>>Shared Memory: Hierarchical 8>>Distributed Memory: Introduction 9>>Hypercube Interconnection Network 10>>Mesh Interconnection Network 11>> Bibliography Introduction to MIMD Architectures
  4. 4. MIMD Architecture Processor A Processor B Processor C Data Input stream A Data Input stream B Data Input stream C Unlike SISD, MISD, MIMD computer works asynchronously. Shared memory (tightly coupled) MIMD Distributed memory (loosely coupled) MIMD Data Output stream A Data Output stream B Data Output stream C Instruction Stream A Instruction Stream B Instruction Stream C MIMD (Multiple Instruction stream, Multiple Data stream) computer system has a number of independent processors operate upon separate data concurrently. Hence each processor has its own program memory or has access to program memory. Similarly, each processor has its own data memory or access to data memory. Clearly there needs to be a mechanism to load the program and data memories and a mechanism for passing information between processors as they work on some problem. MIMD has clearly emerges the architecture of choice for general-purpose mutiprocessors. MIMD machines offer flexibility. With the correct hardware and software support, MIMDs can function as single user machines focusing on high performance for one application, as multiprogrammed machines running many tasks simultaneously, or as some combination of these functions. There are two types of MIMD architectures: distributed memory MIMD architecture, and shared memory MIMD architecture.
  5. 5. 1 MIMD Architecture’s Goal Without accessibility to shared memory architectures, it is not possible to obtain memory access of a remote block in a multicomputer. Rather than having a processor being allocated to different process or having a processor continue with other computations (in other words stall), Distributed MIMD architectures are used. Thus, the main point of this architectural design is to develop a message passing parallel computer system organized such that the processor time spent in communication within the network is reduced to a minimum. II. Components of the MultiComputer and Their Tasks
  6. 6. Within a multicomputer, there are a large number of nodes and a communication network linking these nodes together. Inside each node, there are three important elements that do have tasks related to message passing : a. Computation Processor and Private Memory b. Communication Processor This component is responsible for organizing communication among the multicomputer nodes, "packetizing" a message as a chunk of memory in the on the giving end, and "depacketizing" the same message for the receiving node. c. Router, commonly referred to as switch units The router’s main task is to transmit the message from one node to the next and assist the communication processor in organizing the communication of the message in through the network of nodes. The development of each of the above three elements took place progressively, as hardware became more and more complex and useful. First came the Generation I computers, in which messages were passed through direct links between nodes, but there were not any communication processors or routers. Then Generation II multicomputers came along with independent switch
  7. 7. units that were separate from the processor, and finally in the Generation III multicomputer, all three components exist. III. MultiComputer Classification Schemes One method of classifying a multicomputer’s scheme of message transmission is its interconnection network topology, which in plain English means how the nodes are geometrically arranged as a network. There is great value in this information. The idea behind it is related to the notion in computer science known as the Traveling Salesman problem, the Shortest Path Algorithm from point A to point B(or in this case node A to node B) is directly linked to the shape that the nodes generate when linked together. Interconnection network topology has a great influence on message transmission. Routing Routing is the determination of a path, whether it is the shortest or the longest or somewhere in between, from the source to the destination node. Two broad categories of routing exist--- deterministic and adaptive. In deterministic routing, the path is determined by the source and destination nodes and in adaptive routing the intermediate nodes can "see" a blocked channel on their way to their destination and can reroute to a new path. This works similar to the way people normally alter their paths of traveling when hearing about the accident on I -495. Deterministic routing has two more sub-categories that fall within it. One of them is named is source routing, a method in which the source node determines the routing path to the destination. The other method, distributed routing, considers all intermediate nodes and the source node in determining the best path towards the destination, avoiding blocked channels. THE TYPES OF DETERMINISTIC ROUTING Source Routing Means---- Street Sign Routing Street Sign routing requires that the message header carries the entire path information.
  8. 8. At each turn of the node, the path towards the destination has been predetermined. However each message header also has the capability to choose a default direction in which case an intermediate node’s channel is in use. It does this by comparing the node’s address to see if a miss occurred. Distributed Routing Schemes----- Dimension Ordered Routing Dimension ordered routing is best explained through a diagram provided in Figure 17.14 and is a routing method in which a message moves along a "dimension" until it reaches the a certain coordinate and moves through another dimension. This scheme only works if the source node and destination node lie along different dimensions. Table Lookup Routing In this type of routing, a table is formulated so that any given node can go where to forward its message. Of course, this style of routing eats away at a lot of hardware, but is good in software usage. This is because a very huge lookup table will require a very big chip area.
  9. 9. Shared memory :bus based MIMD machines with shared memory have processors which share a common, central memory. In the simplest form, all processors are attached to a bus which connects them to memory. This setup is called bus-based shared memory. Bus-based machines may have another bus that enables them to communicate directly with one another. This additional bus is used for synchronization among the processors. When using bus-based shared memory MIMD machines, only a small number of processors can be supported. There is contention among the processors for access to shared memory, so these machines are limited for this reason. These machines may be incrementally expanded up to the point where there is too much contention on the bus. Shared Memory: Extended MIMD machines with extended shared memory attempt to avoid or reduce the contention among processors for shared memory by subdividing the memory into a number of independent memory units. These memory units are connected to the processsors by an interconnection network.
  10. 10. The memory units are treated as a unified central memory. One type of interconnection network for this type of architecture is a crossbar switching network. In this scheme, N processors are linked to M memory units which requires N times M switches. This is not an economically feasible setup for connecting a large number of processors. Shared Memory: Hierarchical MIMD machines with hierarchical shared memory use a hierarchy of buses to give processors access to each other's memory. Processors on different boards may communicate through internodal buses. Buses support communication between boards. Wiuth this type of architecture,
  11. 11. the machine may support over a thousand processors. Distributed Memory: Introduction In distributed memory MIMD machines, each processor has its own individual memory location. For data to be shared, it must be passed from one processor to another as a message. Since there is no shared memory, contention is not as great a problem with these machines. It is not economically feasible to connect a large number of processors directly to each other. A way to avoid this multitude of direct connections is to connect each processor to just a few others. This type of design can be inefficient because of the added time required to pass a message from one processor to another along the message path. The amount of time required for processors to perform simple message routing can be substantial. Systems were designed to reduce this time loss and hypercube and mesh are among two of the popular interconnection schemes. Hypercube Interconnection Network In an MIMD distributed memory machine with a hypercube system interconnection network containing four processors, a processor and a memeory module are placed at each vertex of a square. The diameter of the system is the minimum number of steps it takes for one processor to send a message to the processor that is the farthest away. So, for example, the diameter of a 2- cube is 2. In a hypercube system with eight processors and each processor amd memory module
  12. 12. being placed in the vertex of a cube, the diameter is 3. In general, a system that contains 2^N processors with each processor directly connected to N other processors, the diameter of the system is N. One disadvantage of a hypercube system is that it must be configured in powers of two, so a machine must be built that could potentially have many more processors than is really needed for the application. Mesh Interconnection Network In an MIMD distributed memory machine with a mesh interconnection network, processors are placed in a two-dimensional grid. Each processor is connected to its four immediate neighbors. Wraparound connections may be provided at the edges of the mesh. One advantage of the mesh interconnection network over the hypercube is that the mesh system need not be configured in powers of two. A disadvantage is that the diameter of the mesh network is greater than the hypercube for systems with more than four processors. Bibliography with References: This work presented here has been prepared and polished with the help of several sources. I feel it my moral responsibility to express my sincere thanks to the concentrators .I feel extremely obligated to the content creators of these resources and truly appreciate their sprit.
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