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Ieee 2012 titles for vlsi


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Ieee 2012 titles for vlsi

  1. 1. 28,South Usman Road,, TNagar, Chennai-17. Ph : 044-43855940 Mobile : +91-9042085008 Web : email : temasolution@gmail.comS.NO PROJECT TITLE CODE YEAR VLSI 1. Compact Expressions for Supply Noise Induced Period Jitter of Global Binary Clock VLSI01 2012 Trees 2. A Novel Technique for Improving Hardware Trojan Detection and Reducing Trojan VLSI02 2012 Activation Time 3. Reconsidering High-Speed Design Criteria for Transmission-Gate-Based Master– VLSI03 2012 Slave Flip-Flops 4. Hierarchical Design of an Application-Specific Instruction Set Processor for High- VLSI04 2012 Throughput and Scalable FFT Processing 5. Toeplitz Matrix Approach for Binary Field Multiplication Using Quadrinomials VLSI05 2012 6. VL Architecture of Arithmetic Coder Used in SPIHT VLSI06 2012 7. High-Speed Low-Power Viterbi Decoder Design for TCM Decoders VLSI07 2012 8. Loop Acceleration Exploration for ASIP Architecture VLSI08 2012 9. Robust Secure Scan Design Against Scan-Based Differential Cryptanalysis VLSI09 2012 10. A Scalable High-Performance Virus Detection Processor Against a Large Pattern Set VLSI10 2012 for Embedded Network Security 11. Pipelined Parallel FFT Architectures via Folding Transformation VLSI11 2012 12. Scalable Hardware Trojan Diagnosis VLSI12 2012 13. Transactions Briefs: Novel Interpolation and Polynomial Selection for Low- VLSI13 2012 Complexity Chase Soft-Decision Reed-Solomon Decoding 14. A Multi-Resolution Fast Filter Bank for Spectrum Sensing in Military Radio VLSI14 2012 Receivers 15. Optimizing Floating Point Units in Hybrid FPGAs VLSI15 2012 16. Investigating the Impact of Logic and Circuit Implementation on Full Adder VLSI16 2012 Performance 17. Transactions Letters: Highly Scalable Parallel Arithmetic Coding on Multi-Core VLSI17 2012 Processors Using LDPC Codes 18. Synchronous FPGA-Based High-Resolution Implementations of Digital Pulse-Width VLSI18 2012 Modulators 19. FPGA-Based Track Circuit for Railways Using Transmission Encoding VLSI19 2012 20. Nonlinear Trellis Codes for Binary-Input Binary-Output Multiple-Access Channels VLSI20 2012 with Single-User Decoding 21. A Novel All-Digital Multichannel Multimode RF Transmitter Using Delta-Sigma VLSI21 2012 Modulation 22. A Subspace-Based Two-Way Ranging System Using a Chirp Spread Spectrum VLSI22 2012 Modem, Robust to Frequency Offset 23. Parallel Searching-Based Sphere Detector for MIMO Downlink OFDM Systems VLSI23 2012 24. The LUT-SR Family of Uniform Random Number Generators for FPGA VLSI24 2012 Architectures Further more details visit : send your request to :
  2. 2. 28,South Usman Road,, TNagar, Chennai-17. Ph : 044-43855940 Mobile : +91-9042085008 Web : email : temasolution@gmail.com25. Trellis-Search Based Soft-Input Soft-Output MIMO Detector: Algorithm and VLSI VLSI25 2012 Architecture26. VLSI signal processing oriented segmentation based serial parallel multiplier VLSI26 201227. VLSI Architecture of Arithmetic Coder Used in SPIHT VLSI27 201228. VLSI Friendly ECG QRS Complex Detector for Body Sensor Networks VLSI28 201229. VLSI Based Robust Router Architecture VLSI29 201230. An Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Transform VLSI30 201231. A novel VLSI architecture for generation of Six Phase pulse compression sequences VLSI31 201232. VLSI Implementation of Advanced Encryption Standard VLSI32 201233. A Network-Efficient Nonbinary QC-LDPC Decoder Architecture VLSI33 201234. Area-Efficient Parallel FIR Digital Filter Structures for Symmetric Convolutions VLSI34 2012 Based on Fast FIR Algorithm35. Area and power efficient VLSI architecture for DCT VLSI35 201236. CORDIC Designs for Fixed Angle of Rotation VLSI36 201237. Algebraic Soft-Decision Reed–Solomon Decoding VLSI37 201238. Design and Implementation of Block-Based Partitioning for Parallel Flip-Chip Power- VLSI38 2012 Grid Analysis39. Architectural design of a highly programmable Radix-2 FFT processor with efficient VLSI39 2012 addressing logic40. A Continuous-Time Delta-Sigma Modulator for RF Subsampling Receivers VLSI40 201241. Developing ARM based PDA using Inferno OS VLSI41 201242. FPGA-Based High-Performance and Scalable Block LU Decomposition Architecture VLSI42 201243. A High Performance and Memory Efficient LU Decomposer on FPGAs VLSI43 2012 Further more details visit : send your request to :