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  1. 1. Design and Implementation of VLSI Systems (EN1600) Lecture 30: Array Subsystems (DRAM/ROM)S. Reda EN1600 SP’08
  2. 2. Lecture outline • Last time – Memory periphery (row/column circuitry) – Core cell: SRAM cells • This time (different core cells) – DRAM cells – ROM cells – Non Volatile Read Write (NVRW) cellsS. Reda EN1600 SP’08
  3. 3. 3T DRAM cell WWL WWL write RWL Vdd M3 BL1 M1 X M2 X Vdd-Vt Cs RWL read BL2 Vdd-Vt ∆V BL1 BL2  No constraints on device sizes (ratioless)  Reads are non-destructive  Value stored at node X when writing a “1” is VWWL - VtnS. Reda EN1600 SP’08
  4. 4. 1T DRAM Cell WL write read WL “1” “1” M1 X X Vdd-Vt Cs CBL BL Vdd Vdd/2 sensing BL Write: Cs is charged (or discharged) by asserting WL and BL Read: Charge redistribution occurs between CBL and Cs Read is destructive, so must refresh after read Leakage cause stored values to “disappear” → refresh periodicallyS. Reda EN1600 SP’08
  5. 5. The bit line is precharged to VDD/2S. Reda EN1600 SP’08
  6. 6. How DRAM cells are manufactured? Trench capacitorS. Reda EN1600 SP’08
  7. 7. DRAM subarray architectures rejects common mode noise sensitive to noiseS. Reda EN1600 SP’08
  8. 8. ROMs • Read-Only Memories are nonvolatile – Retain their contents when power is removed • Mask-programmed ROMs use one transistor per bit – Presence or absence determines 1 or 0S. Reda EN1600 SP’08
  9. 9. NOR ROMs • 4-word x 6-bit ROM Word 0: 010101 – Represented with dot diagram Word 1: 011001 – Dots indicate 1’s in ROM Word 2: 100101 weak pseudo-nMOS A1 A0 pullups Word 3: 101010 2:4 DEC ROM Array Y5 Y4 Y3 Y2 Y1 Y0 Dot diagram Looks like 6 4-input pseudo-nMOS NORsS. Reda EN1600 SP’08
  10. 10. NAND ROM V DD Pull-up devices BL [0] BL [1] BL [2] BL [3] WL [0] WL [1] WL [2] WL [3] • All word lines high by default with exception of selected row • No transistor with the selected word -> bitline pulled down • Transistor with the selected word -> bitline remain highS. Reda EN1600 SP’08
  11. 11. Non Volatile Read/Write (NVRW) memories • Same architecture as ROM structures • A floating transistor gate is used • similar to traditional MOS, except that an extra polysilicon strip is inserted between the gate and channel • allow the threshold voltage to be progammable Floating gate Gate D Source Drain tox G tox S n+ p n+_ Substrate Device cross-section Schematic symbolS. Reda EN1600 SP’08
  12. 12. Floating gate transistor programming 20 V 0V 5V 20 V -5 V 0V 5V 10V 5V - 2.5 V S D S D S D Avalanche injection Removing programming Programming results in voltage leaves charge trapped higher V T . Process is self-timing Floating gate is surrounded - Effectively increases by an insulator material → Threshold voltage traps the electronsS. Reda EN1600 SP’08
  13. 13. Flash Electrically Erasable ROMs C ontrol gate Floating gate erasure Thin tunneling oxid e n 1 source n 1 d rain programming p- substrate To erase: ground the gate and apply a 12V at the sourceS. Reda EN1600 SP’08
  14. 14. Basic Operations in a NOR Flash Memory― Erase cell array BL 0 BL 1 G 12 V 0V WL 0 S D 0V WL 1 open openS. Reda EN1600 SP’08
  15. 15. Basic Operations in a NOR Flash Memory― Write 12 V BL 0 BL 1 G 6V 12 V WL 0 S D 0V WL 1 6V 0VS. Reda EN1600 SP’08
  16. 16. Basic Operations in a NOR Flash Memory― Read BL 0 BL 1 5V G 1V 5V WL 0 S D 0V WL 1 1V 0VS. Reda EN1600 SP’08