SMP IMPL. ON BSD/MIPS
 - TLB CONSISTENCY -
        syuu1228
• SGI   Octane   OpenBSD/sgi SMP
• OpenBSD   Developer

•                  per-cpu   MP
• pmap(                        )
        MP   = TLB Shootdown

• IPI




   MP               TLB
MMU
            TLB




            MMU




•




•

    TLB
MMU
              TLB




              MMU




•   CPU MMU

•   MMU TLB
      TLB
MMU
                        TLB
           Invalidate


                        MMU




•

    TLB
MP                  TLB
                         TLB
           Invalidate


                         MMU




            ...
CPU


•   CPU


    →

    •


    •


    •
CPU TLB
    INVALIDATE

•                         TLB
     TLB   Invalidate

•

                                →IPI
IPI: INTER PROCESSOR
               INTERRUPT


             CPU0   CPU1




• IPI


•
IPI         TLB INVALIDATE
                                    TLB
                     Invalidate


                     ...
CPU0             CPU1



           IPI


                 TLB Invalidate




                   TLB Miss




•           ...
TLB SHOOTDOWN
•   Mach SMP

•                     CPU

•


    •


    •           IPI         TLB   Invalidate

    •
TLB SHOOTDOWN



      IPI
TLB SHOOTDOWN
•               OS

•


    •




    •




•

    →      OS
MODIFIED TLB SHOOTDOWN

• RP3   Mach

•


    •


    •          TLB Invalidate
MODIFIED TLB SHOOTDOWN



          IPI
MODIFIED TLB SHOOTDOWN



•


•
BSD

•   FreeBSD/mips-current    SMP
    TLB Shootdown

•   Modified TLB Shootdown



•   OpenBSD/sgi

•   MIPS Tagged TLB
Upcoming SlideShare
Loading in …5
×

SMP Impl. on BSD/MIPS - TLB Consistency -

1,551 views

Published on

Published in: Technology
0 Comments
0 Likes
Statistics
Notes
  • Be the first to comment

  • Be the first to like this

No Downloads
Views
Total views
1,551
On SlideShare
0
From Embeds
0
Number of Embeds
7
Actions
Shares
0
Downloads
21
Comments
0
Likes
0
Embeds 0
No embeds

No notes for slide
  • SMP Impl. on BSD/MIPS - TLB Consistency -

    1. 1. SMP IMPL. ON BSD/MIPS - TLB CONSISTENCY - syuu1228
    2. 2. • SGI Octane OpenBSD/sgi SMP
    3. 3. • OpenBSD Developer • per-cpu MP
    4. 4. • pmap( ) MP = TLB Shootdown • IPI MP TLB
    5. 5. MMU TLB MMU • • TLB
    6. 6. MMU TLB MMU • CPU MMU • MMU TLB TLB
    7. 7. MMU TLB Invalidate MMU • TLB
    8. 8. MP TLB TLB Invalidate MMU TLB MMU • CPU TLB • CPU Invalidate
    9. 9. CPU • CPU → • • •
    10. 10. CPU TLB INVALIDATE • TLB TLB Invalidate • →IPI
    11. 11. IPI: INTER PROCESSOR INTERRUPT CPU0 CPU1 • IPI •
    12. 12. IPI TLB INVALIDATE TLB Invalidate MMU IPI TLB Invalidate MMU • IPI Invalidate •
    13. 13. CPU0 CPU1 IPI TLB Invalidate TLB Miss • CPU1
    14. 14. TLB SHOOTDOWN • Mach SMP • CPU • • • IPI TLB Invalidate •
    15. 15. TLB SHOOTDOWN IPI
    16. 16. TLB SHOOTDOWN • OS • • • • → OS
    17. 17. MODIFIED TLB SHOOTDOWN • RP3 Mach • • • TLB Invalidate
    18. 18. MODIFIED TLB SHOOTDOWN IPI
    19. 19. MODIFIED TLB SHOOTDOWN • •
    20. 20. BSD • FreeBSD/mips-current SMP TLB Shootdown • Modified TLB Shootdown • OpenBSD/sgi • MIPS Tagged TLB

    ×