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SMP Impl. on BSD/MIPS - TLB Consistency -

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SMP Impl. on BSD/MIPS - TLB Consistency -

  1. 1. SMP IMPL. ON BSD/MIPS - TLB CONSISTENCY - syuu1228
  2. 2. • SGI Octane OpenBSD/sgi SMP
  3. 3. • OpenBSD Developer • per-cpu MP
  4. 4. • pmap( ) MP = TLB Shootdown • IPI MP TLB
  5. 5. MMU TLB MMU • • TLB
  6. 6. MMU TLB MMU • CPU MMU • MMU TLB TLB
  7. 7. MMU TLB Invalidate MMU • TLB
  8. 8. MP TLB TLB Invalidate MMU TLB MMU • CPU TLB • CPU Invalidate
  9. 9. CPU • CPU → • • •
  10. 10. CPU TLB INVALIDATE • TLB TLB Invalidate • →IPI
  11. 11. IPI: INTER PROCESSOR INTERRUPT CPU0 CPU1 • IPI •
  12. 12. IPI TLB INVALIDATE TLB Invalidate MMU IPI TLB Invalidate MMU • IPI Invalidate •
  13. 13. CPU0 CPU1 IPI TLB Invalidate TLB Miss • CPU1
  14. 14. TLB SHOOTDOWN • Mach SMP • CPU • • • IPI TLB Invalidate •
  15. 15. TLB SHOOTDOWN IPI
  16. 16. TLB SHOOTDOWN • OS • • • • → OS
  17. 17. MODIFIED TLB SHOOTDOWN • RP3 Mach • • • TLB Invalidate
  18. 18. MODIFIED TLB SHOOTDOWN IPI
  19. 19. MODIFIED TLB SHOOTDOWN • •
  20. 20. BSD • FreeBSD/mips-current SMP TLB Shootdown • Modified TLB Shootdown • OpenBSD/sgi • MIPS Tagged TLB

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