If a particular node is missing, it leaves a gap in the address map and any attempte
access to the missing address space returns an address error.
Base Address 12G
addresses Node 2
Base Address 8G
Base Address 4G
Base Address 0
Figure 2-2 Cac Space Addressing
Calias memory space for all nodes is only accessible by the local processor, at physic
address 0 up to Calias size.
Processor 0 Processor 1
Processor Memory Processor Memory
address address address address
Addr = 0x2_0000 Addr = 0x2_0000
Addr = 0x1_0000 0x1_0000 Addr = 0x1_0000 0x0_0000 address
0x0_FFFF 0x1_FFFF spaces
Addr = 0x0_0000 Addr = 0x0_0000
Figure 2-8 Processor 0/1 Address Mapping in Ualias
• Router chip: located on each Router board in CrayLink Interconnect.
• Crossbow chip: located on the midplane as part of the XIO interconnect
• Bridge, LINC, and IOC3 chips: located on XIO boards linked to the I/O interface
IO Figure 3-1 shows interconnections between these ASICs and the communication
protocols that run on the interconnections from the Hub ASIC.
XIO PCI Serial
Processors -Le XIO tocol Ethernet
Memory w- leve Pro yLink
Lo toc Router
To Other HUB
Figure 3-1 ASIC Protocols