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Coa swetappt copy

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Coa swetappt copy

  1. 1. VECTOR PROCESSING Problems that can be efficiently formulated in terms of vectors -Long-range weather forecasting –Petroleum explorations –Seismic data analysis –Medical diagnosis –Aerodynamics and space flight simulations –Artificial intelligence and expert systems –Mapping the human genom –Image processing
  2. 2. Vector Operations • Many scientific problems require arithmetic operations on large arrays of numbers. • These numbers are usually formulated as vectors and matrices of floating-point numbers. • A vector is an ordered set of a one-dimensional array of data items. • A vector V of length n is represented as a row vector by • V = [ V1 V2V3… Vn] • It may be represented as a column vector if the data items are listed in a column. • Operations on vectors must be broken down into single computations with subscripted variables.
  3. 3. Vector Operations • The element Vi of vector V is written as V(I) and the index I refers to a memory address or register where the number is stored. • The difference between a conventional Scalar Processor and a Vector Processor, consider the following Fortran DO loop: • This is program for adding two vectors A and B of length 100 to produce a vector C. • The machine language by the following sequence of operations . • DO 20 I = 1, 100 • 20 C(I) = B(I) + A(I)
  4. 4. Vector Operations • This is program loop that reads a pair of operands from arrays A and B and performs a floating-point addition. • The loop control variable is then updated and the repeat 100 times. • Operations to be specified with a single vector instruction of the form • Initialize I = 020 Read A(I)Read B(I)Store C(I) = A(I) + B(I)Increment I = i + 1If I 100 goto 20ContinueC(1:100) = A(1:100) + B(1:100)
  5. 5. Vector Operations • The vector instruction include the initial address of the operands, the length of the vectors, and the operation to be performed, all in one composite instruction. • The vector instruction format as shown in fig. • A three-address instruction with three fields specifying the base address of the operands and an additional field that gives the length of the data items in the vectors. • Assume the vector operands reside in memory . • To design the processor with a large number of registers and store all operands in registers to the addition operation.The base address and length in the vector instruction specify a group of CPU registers. • Operation codeBase address source 1Base address source 2Base address destinationVector length
  6. 6. Memory Interleaving • Pipelineand vector processorsoften require simultaneous access to memory from two or more sources. • An instruction pipeline may require the fetching of an instruction and an operand at the same time from two different segments. • An arithmetic pipeline usually requires two or more operands to enter the pipeline at the same time. • Memory interleaving is a method to increase the speed of the high end microprocessors and it is even applicable to the hard disks too.
  7. 7. Memory Interleaving • It can be of 2 types: 2 way interleaving(using 2 complete address buses) & 4 way interleaving(using complete 4 address buses). • There is a controller too that generates the addresses. CPU can access alternate sections of memory. • While one section is busy processing upon a word at a particular location, the other section accesses the word at the next location. • Resembling overlapping!!!
  8. 8. Memory Interleaving • Simultaneousaccess to memory from two or more source using one memory bus system • A memory module is a memory array together with its own address and data registers. • Figure shows a memory unit with four modules. • Each memory array has its own address register AR and data register DR. • The address registers receive information from a common address bus and the data registers communicate with a bidirectional data bus. • The 2 bits of the address register can be used to between the 4 memory modules.
  9. 9. Multiple module memory organizations • The load instruction is at address 101 and X is equal to
  10. 10. Memory Interleaving • In an interleaved memory, different sets of addresses are assigned to different memory modules. • For example, in a 2-module memory system, the Even addresses may be in a 1- module and the Odd addresses in the other. • When the number of modules is a power of 2, the least significant bits of the address select a memory module and the remaining bits design the specific location to be accessed within the selected module. • A modular memory useful in systems with pipeline and vector processing. • A vector processor that uses an n-way interleaved memory can fetch n operands from n different modules.
  11. 11. Array Processors • Performs computations on large arrays of data • The term is used to refer to 2 different types of processors. 1)Attached array processor : – Auxiliary processor attached to a general purpose computer – To improve the performance of the host computer in specific numerical computation tasks 2)SIMD array processor : –Computer with multiple processing units operating in parallel • The both types of array processors manipulate vectors , their internal organization is different.
  12. 12. Attached Array Processor • The attached array processor has an input –output interface to a common processor and another interface with a local memory • The local memory interconnects main memory
  13. 13. Attached Array Processor • Figure shows the interconnection of an attached array processor to a host computer. • The host computer is a general purpose computer and the attached processor is a back- end machine driven by the host computer. • The array processor is connected through an input-output controller to the computer and the computer treats an external interface.
  14. 14. SIMD Array Processor • Computer with multiple processing units operating in parallel • The processing units are synchronized to perform the same operation under the control of a common control unit, thus providing a single instruction stream, multiple data stream(SIMD) organization. • A general block diagram of an array processor is shown in figure. • It contains a set of identical processing elements(PEs), each having a local memory M. • Each processor element includes an ALU, a floating-point arithmetic unit, and working registers. • The master control unit controls the operations in the processor elements.
  15. 15. SIMD Array Processor Organization
  16. 16. SIMD Array Processor • The main memory is used for storage of the program. • The function of the master control unit is to decode the instructions and determine how the instruction is to be executed. • Scalar and program control instructions are directly executed within the master control unit. • Each PE uses operands stored in its local memory. • For example, the vector addition C = A + B. • The master control unit first stores the ith components aiof A and B in local memory Mifor i =1,2,3,...,n. • It then floating-point add instruction Ci= ai+ bito all PEs, the addition to take place simultaneously. • The components of are stored in fixed locations in each local memory.
  17. 17. SIMD Array Processor • The components of Ci are stored in fixed locations in each local memory. • This produces the desired vector sum in one add cycle • Masking are used to control the status of each PE during the execution of vector instructions. • Each PE has a flag that is set when the PE is active and reset when the PE is inactive. • Only those PEs that participate are active during the execution of the instruction. • For example, the array processor contains a set of 64 PEs. • If a vector length of less than 64 data items is to be processed , the control unit selects the proper number of PEs to be active.
  18. 18. SIMD Array Processor • Vectors of greater length than 64 must be divided into 64-word portions by the control unit. • The SIMD array processor is the ILLIAC IV computer developed at the University of Illinois and manufactured by the Burroughs Corp. • This computer is no longer in operation. • SIMD processors are highly specialized computers. • They suited for numerical problems that can be expressed in vector or matrix form.

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