Anubhuti - Engineering Incubation Centre (EIC)

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Anubhuti - Engineering Incubation Centre (EIC)

  1. 1. CVC Confidential, www.cvcblr.com
  2. 2. <ul><li>Anubhūti   - a powerful word found in many Indian languages </li></ul><ul><li>Means profound experience leading to self-realization </li></ul><ul><li>In our context – it is beyond simple trainings, a complete Experiential Learning </li></ul>CVC Confidential, www.cvcblr.com VLSI Design & Verification Incubation Transforming Graduates to VLSI Professionals
  3. 3. CVC Confidential, www.cvcblr.com
  4. 4. CVC Confidential, www.cvcblr.com RCG – Recent College Graduate
  5. 6. <ul><li>What is EIC? </li></ul><ul><li>Engineering Incubation Centre </li></ul><ul><li>Formalization of our time-tested internal process </li></ul><ul><li>Bringing up fresh graduates to be productive in VLSI Design & Verification </li></ul><ul><li>PRAGMATIC PROCESS - ALARM </li></ul><ul><li>Assess - Skill level </li></ul><ul><li>Learn - Bridge the gaps </li></ul><ul><li>Adopt - Deploy what you learnt </li></ul><ul><li>Review - Measure the skill set </li></ul><ul><li>Master - Build the confidence </li></ul>CVC Confidential, www.cvcblr.com
  6. 7. <ul><li>Unique Features </li></ul><ul><li>Tailor made to suit individual strengths & weakness; Not a “one size fit all” offering </li></ul><ul><li>Create production quality IPs </li></ul><ul><li>Graduate can choose a dream job, we will guide you on what’s needed to get there. </li></ul><ul><li>Most up-to date content—including what the Design teams require few years down the line </li></ul><ul><li>Covers SystemVerilog 2009 features </li></ul><ul><li>Opportunity to share your ideas/experience through our newsletter </li></ul>CVC Confidential, www.cvcblr.com
  7. 8. <ul><li>Our Team </li></ul><ul><li>Several ASICs designed & verified </li></ul><ul><li>Industry icons; Experienced from spec-to-chips-to-boards </li></ul><ul><li>Active contributor to newer technologies </li></ul><ul><li>Experienced , World Class trainers </li></ul><ul><li>Timelines </li></ul><ul><li>16 weeks (480 hours) </li></ul><ul><li>8 weeks of INDUCTION </li></ul><ul><li>8 weeks of PERFECTION </li></ul><ul><li>Buffer: 2 weeks </li></ul><ul><li>As the strengths of individuals differ!  </li></ul>CVC Confidential, www.cvcblr.com
  8. 9. <ul><li>Phase1 : Introduction </li></ul><ul><li>Recap of Digital System Design </li></ul><ul><li>VLSI Introduction </li></ul><ul><li>VLSI flow </li></ul><ul><li>Phase2 : Building the basics </li></ul><ul><li>UNIX </li></ul><ul><li>Simulation </li></ul><ul><li>Verification </li></ul><ul><li>Synthesis </li></ul><ul><li>Phase3: HDLs </li></ul><ul><li>Verilog HDL </li></ul><ul><li>Simulation wheel </li></ul><ul><li>VHDL </li></ul>CVC Confidential, www.cvcblr.com
  9. 10. <ul><li>Phase4: Art of RTL Design </li></ul><ul><li>Spec —> Micro arch </li></ul><ul><li>Arch —> HDL code </li></ul><ul><li>DIY—1 </li></ul><ul><li>Phase5 : Art of Verification </li></ul><ul><li>Comprehensive Functional Verification </li></ul><ul><li>Toolsmith </li></ul><ul><li>DIY—2 </li></ul><ul><li>Debug, Regressions </li></ul><ul><li>Phase6 : DV Projects </li></ul><ul><li>DVClosure </li></ul><ul><li>DVAuthoring </li></ul><ul><li>SysImplement </li></ul>CVC Confidential, www.cvcblr.com
  10. 11. <ul><li>Phase7 : HDL Synthesis </li></ul><ul><li>Process </li></ul><ul><li>Optimization: area/timing </li></ul><ul><li>HDL Coding Guidelines for Synthesis </li></ul><ul><li>Understanding HDL to HW Mapping </li></ul><ul><li>Phase8: SystemVerilog </li></ul><ul><li>Introduction </li></ul><ul><li>SV-Design </li></ul>CVC Confidential, www.cvcblr.com
  11. 12. <ul><li>Phase9: Assertion Based Verification: </li></ul><ul><li>ABV introduction </li></ul><ul><li>SystemVerilog Assertions </li></ul><ul><li>Formal Verification </li></ul><ul><li>Phase12 : FPGA Prototyping </li></ul><ul><li>Phase16: Domain specific case study </li></ul><ul><li>Networking—Ethernet Switch/Router </li></ul><ul><li>Processor design </li></ul><ul><li>Image processing </li></ul>CVC Confidential, www.cvcblr.com
  12. 13. <ul><li>Phase8: SystemVerilog </li></ul><ul><li>Introduction </li></ul><ul><li>SV-Design </li></ul><ul><li>Phase9: Assertion Based Verification: </li></ul><ul><li>ABV introduction </li></ul><ul><li>SystemVerilog Assertions </li></ul><ul><li>Formal Verification </li></ul><ul><li>Phase10: Verification with SystemVerilog </li></ul><ul><li>Class, OOP </li></ul><ul><li>Coverage, constraints  </li></ul>CVC Confidential, www.cvcblr.com
  13. 14. <ul><li>Phase11: Verification Methodology </li></ul><ul><li>Open Verification Methodology (OVM) </li></ul><ul><li>Verification Methodology Manual (VMM)  </li></ul><ul><li>Elective: </li></ul><ul><li>Phase13 : Property Specification Language </li></ul><ul><li>Phase14 : SystemC </li></ul><ul><li>Phase15: Essential e — IEEE 1647 </li></ul><ul><li>Phase16: Domain specific case study </li></ul><ul><li>Networking—Ethernet Switch/Router </li></ul><ul><li>Processor design </li></ul><ul><li>Image processing </li></ul>CVC Confidential, www.cvcblr.com

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