System Verilog 2009 & 2012 enhancements


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  • The final procedure is like an initial procedure, defining a procedural block of statements, except that it occurs at the end of simulation time and executes without delays. A final procedure is typically used to display statistical information about the simulation.
  • In SystemVerilog2005 $fatal / $error / $warning / $info could only be used in assertions
  • If V(a) < 10.5 mV and b is true, then c is true.
  • The only problem with OO programming is that it is essentially static, and a change in requirements can have a profound impact on development timelines.Aspect-Oriented Programming (AOP) complements OO programming by allowing the developer to dynamically modify the static OO model to create a system that can grow to meet new requirements. Just as objects in the real world can change their states during their lifecycles, an application can adopt new characteristics as it develops.
  • Packages provide a declaration space, which can be shared by other building blocks. Package declarations can be imported into other building blocks, including other packages.SystemVerilog-2009 adds import of local package declarations in module, interface and program headers
  • System Verilog 2009 & 2012 enhancements

    1. 1. Literature review on System Verilog Generations and their updations Subash John CGB0911005 VSD 532 M.Sc. [Engg.] in VLSI System Design Module Title: Full Chip Functional Verification Module Leader: Mr. Padmanaban K. M. S. Ramaiah School of Advanced Studies 1
    2. 2. Contents• Introduction• SV 2009 enhancements• SV2012 enhancements• Summary• Conclusion• References M. S. Ramaiah School of Advanced Studies 2
    3. 3. Introduction• SystemVerilog is a combined Hardware Description Language and Hardware Verification Language based on extensions to Verilog• Bulk of the verification functionality is based on the Open Vera language donated by Synopsys• In 2005 there were separate standards for Verilog and SystemVerilog which are merged here with SystemVerilog IEEE 1800-2009.• There are 40+ noticeable new constructs and 25+ system task are introduced in SystemVerilog 2009• The emerging IEEE 1800 2012 has not been officially approved yet M. S. Ramaiah School of Advanced Studies 3
    4. 4. 2009 Enhancements Final block final begin $display("Number of cycles executed %d",$time/period); $display("Final PC = %h",PC); end Bit Selects & Part Selects of Expressions SV2005 SV2009 logic [7:0] tmp; assign tmp = (a & b) | c; assign y = {(a & b) | c}[4:2]; assign y = tmp[4:2]; Edge Event for DDR Logicalways_ff @(posedge clk, negedge rst_n) always_ff @(edge clk, negedge rst_n) always_ff @(clk, negedge rst_n) M. S. Ramaiah School of Advanced Studies 4
    5. 5. Fork-Join enhancementinitialfork begin # 5 $display (“First process”); #10 $display (“Second process”); endjoin join_any join_none$display (“Third process”);Outputs: Outputs: Outputs:#5 First process #5 First process #0 Third process#10 Second process #5 Third process #5 First process#10 Third process #10 Second process #10 Second process M. S. Ramaiah School of Advanced Studies 5
    6. 6. Display Enhancements System Verilog 2005 System Verilog 2009function void check_output; function void check_output;if (marks==40) if (marks==40) $display("PASS: y=%h", y); $info("PASS: y=%h", y);else else $display("FAIL: y=%h , y); $error("FAIL: y=%h , y);endfunction endfunctionIn SystemVerilog2009 $fatal / $error / $warning / $info can be usedanywhere $display can be used M. S. Ramaiah School of Advanced Studies 6
    7. 7. Timescale directive`timescale 10 ns / 1 nsmodule test; a) The value of parameter d is rounded fromlogic set;parameter d = 1.55; 1.55 to 1.6 according to the time precision.initial b) The time unit of the module is 10 ns, and thebegin precision is 1 ns; therefore, the delay of #d set = 0; #d set = 1; parameter d is scaled from 1.6 to 16.end c) #16ns set=0; #32ns set=1.endmoduleSystem Verilog 2005 System Verilog 2009timeunit 100ps; timeunit 100ps/100ps;timeprecision 100ps; M. S. Ramaiah School of Advanced Studies 7
    8. 8. 2012 EnhancementsPROBLEM: enums cannot be extended like classes. As a result:• User needs to take care that enum values do not overlap• User needs to conditionally cast values• User needs to conditionally use the .name() enum method.PROPOSAL• Allow reference to an enum inside the definition of a new enumEXAMPLE:• Extension of an enum defined in class A inside the class B. class A; typedef enum { READ=0, WRITE=1} AType; class B; typedef enum { A::AType, NOACC} Btype; M. S. Ramaiah School of Advanced Studies 8
    9. 9. Scale factors for real constants & Mixed signal assertionsPROBLEM: SystemVerilog does not provide support for scale factors on real constants.• Scale factors are a convenient shorthand when working with real constants.• Adding scale factors to SystemVerilog aids with SV-VAMS integration.PROPOSAL:• Add Verilog-AMS compatible scale factors to SystemVerilog. Scale factors for real constants Mixed-signal assertion features real r1 = 1.6M; // M = 1e6 assert property ( real r2 = 1.2m; // m = 1e-3 (V(a) < 10.5m) & b |-> c real r3 = 1.8n; // n = 1e-9 ); M. S. Ramaiah School of Advanced Studies 9
    10. 10. Aspect oriented support in SVPROBLEM:• Even if some aspect-orientated programming (AOP) features can be implemented using object-orientated programming (OOP) techniques, it is very helpful in some cases to have AOP within an OOP language.Adding AOP to SV can:(1) Enable fast fix path for late testbench changes – Allows an aspect to alter the behavior of the base code – Adding or overriding constraints defined in a class/class methods(2) Enable hot fixes on provided infrastructurePROPOSAL:• Add new language constructs to support aspect-oriented programming M. S. Ramaiah School of Advanced Studies 10
    11. 11. Illustration of AOPOOP AOPclass new_pkt extends pkt; extends test_aop(pkt);constraint c { constraint test0_aop {pkt_length inside pkt_length inside {[100:300]}; {[100:200]}; }} endextendsendclassclass test ; Benefits in AOP in Test Casestask run(my_env env) ; • Allows for scaling and reuse of environmentnew_pkt pkt = new; • Fully backwards compatible with;endtask: run • Effective and efficient method of test writingendclass: test M. S. Ramaiah School of Advanced Studies 11
    12. 12. X-Optimism/Pessimism Removal (1/2)PROBLEM: X-optimism/pessimism is a long-suffered problem in Verilog,SystemVerilog and VHDL• X-detection in testing expressions –Trap the „X‟• X-assignments if X-detection occurs – Propagate the „X‟• Unwanted X-propagation is a 4-state simulation artifact,not a synthesis problemPROPOSAL: Five new X-procedure keywordsinitialx, alwaysx, always_combx, always_ffx, always_latchx M. S. Ramaiah School of Advanced Studies 12
    13. 13. X-Optimism/Pessimism Removal (2/2) always_combx begincase (instr) match = 0;16h014F: match = 1b1; unique0 case (instr)16h152E: match = 1b1; 16h014F: match = 1;<...> 16h152E: match = 1;default: match = 1b0; <...>endcase endcase endif instr goes to X, match is set always_combx for undefinedto 0 instr cases sets match=Xalways_ff @(posedge clk or negedge rst_n)if (!rst_n) q <= 0;else q <= d; if rst_n uninitialized to X, set q to dalways_ffx @(posedge clk or negedge rst_n)if (!rst_n) q <= 0; always_ffx for undefinedelse q <= d; rst_n signal sets q=X M. S. Ramaiah School of Advanced Studies 13
    14. 14. Signed OperatorsPROBLEM:No such thing as signed data types?Does not exist in real hardware! Unsigned multiplication: prod = a * b; Unsigned addition: sum = a + b + ci;PROPOSAL: Create signed operatorsSigned multiplicationprod = a <*> b; No signed data types requiredSigned addition:sum = a <+> b <+> ci; Closer to real hardware M. S. Ramaiah School of Advanced Studies 14
    15. 15. High-level problems (solutions not yet proposed)PROBLEM: Enable assertions to be used in classes.PROBLEM: Facilitate multiple inheritance for classes.PROBLEM: Provide dynamic memory consumption debug constructs.PROBLEM: Adopt the (upcoming) UVM macros into SystemVerilog.PROBLEM: Form new technical committee for synthesizable SystemVerilog.PROBLEM: Improve interaction between SystemVerilog and C/C++from both a data structure perspective and a method calling perspective. M. S. Ramaiah School of Advanced Studies 15
    16. 16. Summary• Using SystemVerilog constructs, makes the designers intent clear resulting in an optimized logic when compared to using Verilog constructs• Newer constructs in SystemVerilog (taken from C++/Open Vera) eliminates the need for knowledge of multiple languages• Design, testbench and assertion features need continued care and improvement to meet users‟ verification challenges M. S. Ramaiah School of Advanced Studies 16
    17. 17. References[1] Cummings and Sutherland (2009) „SystemVerilog Is Getting Even Better!‟ available from < Verilog_Update_Part1_SutherlandHDL.pdf>Retrieved on 26th Feb 2012[2] Accellera Organization (2004) „SystemVerilog 3.1a Language Reference Manual‟ [online] available from <> Retrieved on 26th Feb 2012[3] IEEE Computer Society (2009) „IEEE Standard for SystemVerilog-Unified Hardware Design, Specification, and Verification Language‟ [online] available from < =5985443 > Retrieved on 26th Feb 2012 M. S. Ramaiah School of Advanced Studies 17
    18. 18. Thank YouM. S. Ramaiah School of Advanced Studies 18
    19. 19. RemarksSl. No. Topic Max. marks Marks obtained 1 Quality of slides 5 2 Clarity of subject 5 3 Presentation 5 4 Effort and question handling 5 Total 20 M. S. Ramaiah School of Advanced Studies 19
    20. 20. Package Enhancementspackage data_pkg; typedef logic [7:0] data_t; typedef logic clk_t;endpackage module registerpackage bit_pkg; typedef bit clk_t; import bit_pkg :: rst_t, data_pkg :: *; typedef bit rst_t; (output data_t q,endpackage input data_t d, input clk_t clk,module register (output data_pkg::data_t q, input rst_t rst_n);input data_pkg::data_t d, ...input data_pkg::clk_t clk, endmoduleinput bit_pkg::rst_t rst_n);...endmodule M. S. Ramaiah School of Advanced Studies 20