Interrupts

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Interrupts

  1. 1. Interrupts Eman Aboelatta Copyright © 2012 Embedded Systems Committee
  2. 2. Agenda: • • • • • • • • • • Introduction Interrupts Interrupt sequence So how to we define an ISR? Interrupt Vector Table Modifying Interrupt Vector Table of ATmega16 Registers Used Interrupt priorities Interrupt nesting Nested Interrupt Priorities Copyright © 2012 Embedded Systems Committee
  3. 3. Introduction: At first we have two methods for receiving data or get status Polling Interrupt Copyright © 2012 Embedded Systems Committee
  4. 4. Introduction:con’t Polling : which involves reading the status of the port at fixed intervals to determine whether any data has been received or a change of status has occurred. If so, then we can branch to a routine to service the ports requests. oTakes CPU time even when no requests pending. oOverhead. “Polling is like picking up your phone every few seconds to see if you have a call. …” Other alternative would be to use Interrupts. Copyright © 2012 Embedded Systems Committee
  5. 5. Interrupts (IR):  Interrupts can be used to interrupt the sequential execution of the program flow(called asynchronous processing - that is, we are processing the interrupt events outside the regular execution of the main program.)  Interrupt sources can be - external events (e.g. change of signal at PORTB2). - internal events. Hardware interrupt (e.g. timer overflow). Software interrupt (which occur in response to a command issued in software-Exception Handling ) Copyright © 2012 Embedded Systems Committee
  6. 6. Interrupts (IR):con’t Non Maskable Interrupts : doesn’t depend on global interrupt enable in processor status word Usually it’s external interrupt(Ex : Reset). Maskable Interrupts: Depends on global interrupt enable in processor status word May be : External interrupt from external pin Internal interrupt from peripheral Copyright © 2012 Embedded Systems Committee
  7. 7. Interrupts (IR):Con’t   In the case of an interrupt event the execution of the main routine is interrupted and the interrupt service routine (ISR) of the according event is executed. After executing the ISR the execution proceeds where it has been interrupted. Copyright © 2012 Embedded Systems Committee
  8. 8. Interrupt sequence: When the CPU detects The CPU finishes its current instruction. The contents of the program counter and the condition code register(status register or Processor status word) are pushed onto the stack(because the interrupt routine will almost certainly modify the condition code bits). Further interrupts are disabled to avoid an interrupt being interrupted. The CPU deals with the cause of the interrupt by executing a program called an interrupt handler(ISR)(Interrupt service routine). The CPU executes a return from interrupt instruction at the end of the interrupt handler. Executing this instruction pulls the PC and PSW off the stack and execution then continues normally—as if the interrupt had never happened. Copyright © 2012 Embedded Systems Committee
  9. 9. Interrupt sequence: con’t o PSR : Processor Status Register ==status register==Condition Code register o PC : Program Counter (contains Address of next instruction to be executed) Copyright © 2012 Embedded Systems Committee
  10. 10. So how to we define an ISR? For an ISR to be called, we need three conditions to be true: Firstly, the AVR's global Interrupts Enable bit (I) must be set in the MCU control register SREG. Secondly, the individual interrupt source's enable bit must be set. Each interrupt source has a separate interrupt enable bit in the related peripheral's control registers, which turns on the ISR for that interrupt. Thirdly, The condition for the interrupt must be met - for example, for the USART Receive Complete (USART RX) interrupt, a character must have been received(i.e flag that indicate interrupt raised) Copyright © 2012 Embedded Systems Committee
  11. 11. So how to we define an ISR?con’t Enable Global interrupt (I) Execute ISR Enable peripheral interrupt Interrupt occurred (flag raised) Copyright © 2012 Embedded Systems Committee
  12. 12. • Constant table in ROM. • Special addresses with respect to CPU. • Each interrupt has specific address in interrupt vector table . • This specific address should be programmed to have the address of ISR of this interrupt. • At interrupt processing PC will contain this address or it will be an instruction to jump to this address Copyright © 2012 Embedded Systems Committee
  13. 13. Interrupt Vector Table:cont • From Datasheet ATmega32/16. Copyright © 2012 Embedded Systems Committee
  14. 14. Modifying Interrupt Vector Table of ATmega16:  Assembly  .org $000 rjmp Reset . . . . . Reset: //instructions C ISR ({Vector Source}_vect) { // ISR code to execute here } Copyright © 2012 Embedded Systems Committee
  15. 15. Registers Used Status Register (SREG):To Enable Global Interrupt • The status register contains: – Six bits status indicators ( Z,C,H,V,N,S ) – One bit for global interrupt enable ( I ) • The status bits reflect the results of CPU operation as it executes instructions Copyright © 2012 Embedded Systems Committee
  16. 16. Registers Used with Atmega32/16: To Set/Clear global interrupt enable: • Set global interrupt enable: (Allow) • Clear global interrupt enable: (prevent) The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. Copyright © 2012 Embedded Systems Committee
  17. 17. Registers Used with Atmega32/16: GICR (General Interrupt Control Register):P.no 47 Copyright © 2012 Embedded Systems Committee
  18. 18. Registers Used with Atmega32/16: MCUCR (MCU Control Register) P.66 Copyright © 2012 Embedded Systems Committee
  19. 19. Registers Used with Atmega32/16: MCUCSR (MCU Control and Status Register) P67 Copyright © 2012 Embedded Systems Committee
  20. 20. Registers Used with Atmega32/16: GIFR (General Interrupt Flag Register) Copyright © 2012 Embedded Systems Committee
  21. 21. Defining ISR : • ISR(Interrupt Service Routine) #include <avr/interrupt.h> ISR({Vector Source}_vect) { // ISR code to execute here } Copyright © 2012 Embedded Systems Committee
  22. 22. Interrupt priorities: • Each interrupt has default priority by its location in interrupt vector table • Some controllers provide more intelligent interrupt controller which give interrupt priority level for each interrupt • If two interrupts have a same priority level then the rule to return to the default priority Copyright © 2012 Embedded Systems Committee
  23. 23. Interrupt nesting: • Interrupt Nesting: ability to leave the current interrupt and serve another interrupt • Usually done if global interrupt is enabled and this interrupt has more priority • Some controllers support the nesting of context switching in hardware and others leave it to be done in software Copyright © 2012 Embedded Systems Committee
  24. 24. Nested Interrupt Priorities: Copyright © 2012 Embedded Systems Committee
  25. 25. References • ATmega16 Datasheet. • http://www.avrfreaks.net/ Copyright © 2012 Embedded Systems Committee
  26. 26. info@escommittee.net Copyright © 2012 Embedded Systems Committee

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