• FloorPlanning :
1. Estimate the sizes and set the initial
relative locations of the various blocks in
2. Allocate space for clock and power
3. Decide on the location of the I/O and
•Defines the location of logic cells.
•Sets space for the inter-connect to
each logic cell.
•Assigns each logic cell to a
position in a row.
•Makes the connections
between logic cells.
•Global routing : Determines
where the inter-connections
between the placed logic cells and
blocks will be placed.
•Local Routing: Joins the logic
cells with interconnects.
Goal: Calculate the sizes of all the blocks and assign them locations.
Objectives: Keep the highly connected blocks close.
Goal: Assign the interconnect areas and the location of the logic cells.
Objectives: Minimize the ASIC area and the interconnect density.
• Global Routing:
Goals: Determine the location of all the inter-connects.
Objectives: Minimize the total interconnect area used.
• Detailed Routing:
Goals: Completely route all the interconnect on the chip.
Objectives: Minimize the total interconnect length used.
Our Dear tool : Silicon Ensemble
• LEF: Cell boundaries, pins, routing layer
(metal) spacing and connect rules.
• DEF: Contains netlist information, cell
placement, cell orientation, physical
• GCF: Top-level timing constraints handed
down by the front end designer are handed
to the SE, using PEARL.
The files required
• Pre-running file:
se.ini- initialization file for SE.
• Create the following directories:
lef, def, verilog (netlist) , gcf.
• Type seultra –m=300 &, opens SE in graphical
Importing required files
• Import LEF (in the order given):
header.lef, xlitecore.lef, c8d_40m_dio_00.lef
• Import gcf file:
• Import verilog netlist, xlite_core.v,
• Import the gcf file as system constraints
• Import the .def file for the floor-planning
Structure of a Die
• A Silicon die is mounted inside a chip package.
• A die consists of a logic core inside a power ring.
• Pad-limited die uses tall and thin pads which
maximises the pads used.
• Special power pads are used for the VDD and
• One set of power pads supply one power ring that
supplies power to the I/O pads only: Dirty Power.
• Another set of power pads supply power to the
logic core: Clean Power.
• Dirty Power: Supply large transient
current to the output transistor.
• Avoids injecting noise into the internal
• I/O Pads can protect against ESD as it
has special circuit to protect against
very short high voltage pulses.
• PAD limited design: The number of PADS
around the outer edge of the die determines
the die size , not the number of gates.
• Opposite to that we have a core-limited
Concept of clock Tree
A1, B1, C1
D1, D2, E1
D3, E2, F1
C1 C2 C3
An important result:
The delay through a chain of CMOS gates is minimized when the
ratio between the input capacitance C1 and the load C2 is about 3.
Clock and the cells
• All clocked elements are driven from one
net with a clock spine, skew is caused by
differing interconnect delays and loads
• If the clock driver delay is much larger than
the inter-connect delay, a clock spline
achieves minimum skew but with latency.
• Spread the power dissipation through the
• Balance the rise and the fall time.
• Row based ASICS.
• Interconnects run in horizontal and vertical
• Channel Capacity: Maximum number of
• Row Utilization
• Arrange the logical cells within the flexible
• Minimize the critical net delay.
• Chip as dense as possible
• Minimize the power dissipation
• Minimize cross talk
• Very hard : minimize interconnect length,
meet timing requirement for critical length and
minimize the interconnect congestion.
Timing Driven Placements
• Estimate delay for every net in every trial
• We may estimate length but layers and vias
are not known.
• Hence estimate the RC values.
• But still the results are satisfactory.
• Minimize the interconnect length.
• Maximize the probability that the detailed
router can completely finish the job.
• Minimize the critical path delay.
Conclusion: Our backend flow
1. Loading initial data.
3. I/O Placing
4. Planning the power routing : Adding Power rings , stripes
5. Placing cells
6. Placing the clock tree.
7. Adding filler cells.
8. Power routing : Connect the rings to the follow pins of the cells.
9. Routing ( Global and final routing )
10. Verify Connectivity, geometry and antenna violations.
11. Physical verification (DRC and LVS check using Hercules).
12. Best of luck in the Lab