PHASE CHANGE MEMORY

Ovonic Unified Memory
DEPT. OF E & C., GECH. 2013 Page 1
VISVESVARAYA TECHNOLOGICAL UNIVERSITY
BELGAUM-590014
Technical Seminar Report on
OVONIC UNIFIED MEMORY
Submitted in partial fulfillment of the requirements for the award of degree
BACHELOR OF ENGINEERING
IN
ELECTRONICS AND COMMUNICATION ENGINEERING
BY
SRINIVAS H.V
(4GH09EC046)
Under the guidance of
Mrs. SHRUTHI K.N.B.E., M.TECH.
Assistant Professor
DEPT OF E & C
GEC.HASSAN-573 201
Department of Electronics and Communication Engineering
GOVERNMENT ENGINEERING COLLEGE
Dairy Circle, Hassan - 573201
2012-2013

GOVERNMENT ENGINEERING COLLEGE
DAIRY CIRCLE, HASSAN-573201
Department of Electronics and Communication Engineering
CERTIFICATE
This is to certify that the seminar work entitled “OVONIC UNIFIED
MEMORY” carried out by SRINIVAS H.V, with USN - 4GH09EC046is a bonafide
student of Government Engineering College, Hassan in partial fulfillment of
requirements as part of the VIII semester Technical Seminar prescribed by the
Visvesvaraya Technological University, Belgaum during the academic year 2012-2013.
It is certified that, all corrections/suggestions indicated for Internal Assessment have been
incorporated in the report deposited in the departmental library. The project report has
been approved as it satisfies the academic requirements with respect of seminar
prescribed for the said Degree.
Seminar Guide Seminar Coordinator
--------------------------------------------- -----------------------------------------
Mrs. SHRUTHI K.N. B.E., M.TECH. Mrs. PALLAVI H.V. B.E., M.TECH,
.LMISTE
Assistant Professor Associate Professor
DEPT.OF E& C DEPT.OF E& C
GECH-573 201 GECH-573 201
Name and Signature of HOD
--------------------------------------------
Dr. PARAMESH B.E., M.TECH. , Ph.D.
Professor and Head
DEPT. OF E & C
GECH-573201

ACKNOWLEDGEMENT
I wish to express my thanks to beloved PRINCIPAL DR.KARISIDDAPPA, for
encouragement throughout my studies.
I express my gratitude to DR.PARAMESH, PROFESSOR AND HEAD, dept. of
Electronics and Communication Engineering, for his encouragement and support
throughout my work.
I also express my warm gratitude to MRS. PALLAVI H.V., ASSOCIATE
PROFESSOR, dept. of Electronics and Communication Engineering, for her great
support during the preparation of seminar and also in helping in curricular activities.
At the outset I express my most sincere grateful thanks to my seminar guide,
MRS. SHRUTHI K.N., ASSISTANT PROFESSOR, dept. of Electronics and
Communication Engineering for continuous support and advice not only during the
course of my seminar but also during the period of my stay in GECH.
I also gratefully thank to the holy sanctum “GOVERNMENT
ENGINEERINGCOLLEGE, HASSAN” the temple of learning, for giving me an
opportunity to pursue the degree course in Electronics and Communication Engineering
thus help in shaping my carrier.
Finally I express my gratitude to all teaching staff of dept. of Electronics and
Communication Engineering, my classmates and my parents for their timely support and
suggestions.
I am conscious of the fact that I have received co-operation in many ways from
the teaching and non-teaching staff of the dept. of Electronics and Communication
Engineering and I am grateful to all of their co-operation and their guidance in
completing the task well in time. I thank once again to one and all who have been helped
me in one or the other way in completing my seminar in time.
SRINIVAS H.V
(4GH09EC046)

ABSTRACT
Nowadays, digital memories are used in each and every fields of day-to-day life.
Semiconductors form the fundamental blocks of the modern electronic world providing
the brains and the memory of products all around us from washing machines to super
computers. But now we are entering an era of material limited scaling. Continuous
scaling has required the introduction of new materials.
Current memory technologies have a lot of limitations. The new memory
technologies have got all the good attributes for an ideal memory. Among them Ovonic
Unified Memory (OUM) is the most promising one. OUM is a type of nonvolatile
memory, which uses chalcogenide materials for storage of binary data. The term
chalcogen refers to the Group VI elements of the periodic table. Chalcogenide refers to
alloys containing at least one of these elements such as the alloy of germanium, antimony
and tellurium, which is used as the storage element in OUM. Electrical energy (heat) is
used to convert the material between crystalline (conductive) and amorphous (resistive)
phases and the resistive property of these phases is used to represent 0s and 1s.
To write data into the cell, the chalcogenide is heated past its melting point and
then rapidly cooled to make it amorphous. To make it crystalline, it is heated to just
below its melting point and held there for approximately 50ns, giving the atoms time to
position themselves in their crystal locations. Once programmed, the memory state of the
cell is determined by reading its resistance.

LIST OF FIGURES
FIGURE 5.1 Structural states of chalcogenide alloy 12
FIGURE 5.2 Temperature profile 13
FIGURE 5.3 OUM Architecture 14
FIGURE 6.1 Temperature v/s time plot 16
FIGURE 6.2 Resistance v/s pulse width plot 17
FIGURE6.3 V-I Characteristics 17
FIGURE 6.4 R-I Characteristics 18
FIGURE 7.1 Integration with CMOS 19
FIGURE 7.2 V-I Characteristics 20
FIGURE 7.3 R-I Characteristics 21
FIGURE 7.4 Drain current v/s gate voltage plot 22
FIGURE 9.1 Ternary system 24

CONTENTS
CERTIFICATE ii
ACKNOWLEDGEMENT iii
ABSTRACT iv
LIST OF FIGURES v
CHAPTER 1 INTRODUCTION 1-2
CHAPTER 2 HISTORY OF OUM 3-4
CHAPTER 3 PRESENT MEMORY TECHNOLOGY SCENARIO 5
3.1 Review of memory basics 5-6
3.2 Memory device characteristics 6
3.2.1 Cost 6
3.2.2 Access time and access rate 6-7
3.2.3 Access mode-random and serial 7-8
3.2.4 Alterability-ROMS 8
3.2.5 Permanence of storage 8-9
3.2.6 Cycle time and data transfer rate 9
CHAPTER 4 EMERGING MEMORY TECHNOLOGIES 10
4.1 Fundamental ideas of emerging memories 10-11
CHAPTER 5 OVONIC UNIFIED MEMORY TECHNOLOGY 12-14
5.1 OUM Attributes 14
5.2 OUM Architecture 14-15
CHAPTER 6 BASIC DEVICE OPERATION 16
6.1 Technology and performance 16-17
6.2 V-I Characteristics 17-18
6.3 R-I Characteristics 18
CHAPTER 7 INTEGRATION WITH CMOS 19-22

CHAPTER 8 ADVANTAGES AND RISK FACTORS OF OUM 23
CHAPTER 9 ABOUT CHALCOGENIDE ALLOY 24
9.1 Comparison of amorphous and crystalline state 24
9.2 Test results 24-25
CONCLUSION 26
REFERENCES 27

CHAPTER 1
INTRODUCTION
We are now living in a world driven by various electronic equipments.
Semiconductors form the fundamental building blocks of the modern electronic world
providing the brains and the memory of products all around us from washing machines to
super computers. Semiconductors consist of array of transistors with each transistor being
a simple switch between electrical 0 and 1. Now often bundled together in their 10‟s of
millions they form highly complex, intelligent, reliable semiconductor chips, which are
small and cheap enough for proliferation into products all around us.
Identification of new materials has been, and still is, the primary means in the
development of next generation semiconductors. For the past 30 years, relentless scaling
of CMOS IC technology to smaller dimensions has enabled the continual introduction of
complex microelectronics system functions. However, this trend is not likely to continue
indefinitely beyond the semiconductor technology roadmap. As silicon technology
approaches its material limit, and as we reach the end of the roadmap, an understanding
of emerging research devices will be of foremost importance in the identification of new
materials to address the corresponding technological requirements.
If scaling is to continue to and below the 65nm node, alternatives to CMOS
designs will be needed to provide a path to device scaling beyond the end of the roadmap.
However, these emerging research technologies will be faced with an uphill technology
challenge. For digital applications, these challenges include exponentially increasing the
leakage current (gate, channel, and source/drain junctions), short channel effects, etc.
while for analogue or RF applications, among the challenges are sustained linearity, low
noise figure, power added efficiency and transistor matching. One of the fundamental
approaches to manage this challenge is using new materials to build the next generation
transistors.
Almost 25% of the world wide chip markets are memory devices, each type used
for their specific advantages: the high speed of an SRAM, the high integration density of
a DRAM, or the nonvolatile capability of a FLASH memory device.
The industry is searching for a holy grail of future memory technologies to service
the upcoming market of portable and wireless devices. These applications are already

available based on existing memory technology, but for a successful market penetration.
A higher performance at a lower price is required. The existing technologies are
characterized by the following limitations. DRANs are difficult to integrate. SRAMs are
expensive. FLASH memory can have only a limited number of read and write cycles.
EPROMs have high power requirement and poor flexibility.
There is a growing need for nonvolatile memory technology for high density
standalone embedded CMOS application with faster write speed and higher endurance
than existing nonvolatile memories. OUM is a promising technology to meet this need.
R.G.Neale, D.L.Nelson and Gorden.E.Moore originally reported a phase-change memory
based on chalcogenide materials in 1970. Improvements in phase-change materials
technology subsequently paved the way for development of commercially available
rewriteable CDs and DVD optical memory disks. These advances, coupled with
significant technology scaling and better understanding of the fundamental electrical
device operation, have motivated development of the OUM technology at the present day
technology node.
Ovonic Unified Memory (OUM) is the nonvolatile memory that utilizes a
reversible structural phase change between amorphous and polycrystalline states in a
GeSbTe chalcogenide alloy material. This transition is accomplished by heating a small
volume of the material with a write current pulse and results in a considerable change in
alloy resistivity. The amorphous phase has high resistance and is defined as the RESET
state. The low resistance polycrystalline phase is defined as the SET state.

CHAPTER 2
HISTORY OF OVONIC UNIFIED MEMORY (OUM)
In the 1960s, Stanford R. Ovshinsky of Energy Conversion Devices first
explored the properties of chalcogenide glasses as a potential memory technology. In
1969, Charles Sie published a dissertation, at Iowa State University that both described
and demonstrated the feasibility of a phase change memory device by integrating
chalcogenide film with a diode array. A cinematographic study in 1970 established that
the phase change memory mechanism in chalcogenide glass involves electric-field-
induced crystalline filament growth. In the September 1970 issue of Electronics, Gordon
Moore co-founder of Intel published an article on the technology. However, material
quality and power consumption issues prevented commercialization of the technology.
More recently, interest and research have resumed as flash and DRAM memory
technologies are expected to encounter scaling difficulties as chip lithography shrinks.
The crystalline and amorphous states of chalcogenide glass have dramatically
different electrical resistivity. The amorphous, high resistance state represents a binary 1,
while the crystalline, low resistance state represents a 0. Chalcogenide is the same
material used in re-writable optical media (such as CD-RW and DVD-RW). In those
instances, the material's optical properties are manipulated, rather than its electrical
resistivity, as chalcogenide refractive index also changes with the state of the material.
Magnetic Random Access Memory (MRAM), a technology first developed in
the 1970's, but rarely commercialized, has attracted by the backing of I.B.M, Motorola
and others. MRAM stores information by flip flopping two layers of magnetic material in
and out of alignment with an electric current. For reading and writing data, MRAM can
be as fast as a few nanoseconds, or billionths of a second, best among the next three
generation memory candidates. And if promises to integrate easily with the industry's
existing chip manufacturing process. MRAM is built on top of silicon circuitry. The
biggest problem with MRAM is a relatively small distance, difficult to detect, between its
ON and OFF states.
The second potential successor to flash, Ferro-electric Random Access Memory
(FeRAM / FRAM), has actually been commercially available for nearly 15 years, has
attracted by the backing of Fujitsu, Matsushita, I.B.M. and Ramtron. FRAM relies on the

polarization of what amount to tiny magnets inside certain materials like perouikite, from
basaltic rocks. FRAM memory cells do not wear out until they have been read or written
to billions of times, while MRAM and OUM would require the addition of six to eight
"masking" layers in the chip manufacturing process, just like Flash, FRAM might require
as little as two extra layers.
OVONIC UNIFIED MEMORY is based on the information storage technology
developed by Mr. Ovshinsky that allows rewriting of CD's and DVD's. While CD and
DVD drives read and write ovonic material with lasers, OUM uses electric current to
change the phase of memory cells. These cells are either in crystalline state, where
electrical resistance is low or in amorphous state, where resistance is high. OUM can be
read and write to trillionths of times making its use essentially nondestructive, unlike
MRAM or FRAM. OUM's dynamic range, difference between the electrical resistance in
the crystalline state and in the amorphous state-is wide enough to allow more than one set
of ON and OFF values in a cell, dividing it in to several bits and multiplying memory
density by two, four potential even 16 times. OUM is not as fast as MRAM. The OUM
solid-state memory has cost advantages over conventional solid-state memories such as
DRAM or Flash due to its thin-film nature, very small active storage media, and simple
device structure. OUM requires fewer steps in an IC manufacturing process resulting in
reduced cycle times, fewer defects, and greater manufacturing flexibility.

CHAPTER 3
PRESENT MEMORY TECHNOLOGY SCENARIO
As stated, revising the memory technology fields ruled by silicon technology is of
great importance. Digital Memory is and has been a close comrade of each and every
technical advancement in Information Technology. The current memory technologies
have a lot of limitations. DRAM is volatile and difficult to integrate. RAM is high cost
and volatile. Flash has slower writes and lesser number of write / erase cycles compared
to others. These memory technologies when needed to expand will allow expansion only
two-dimensional space. Hence area required will be increased. They will not allow
stacking of one memory chip over the other. Also the storage capacities are not enough to
fulfill the exponentially increasing need. Hence industry is searching for “Holy Grail”
future memory technologies that are efficient to provide a good solution. Next generation
memories are trying tradeoffs between size and cost. These make them good possibilities
for development.
3.1 Review of memory basics
Every computer system contains a variety of devices to store the instructions and
data required for its operation. These storage devices plus the algorithms needed to
control or manage the stored information constitute the memory system of the computer.
In general, it is desirable that processors should have immediate and interrupted access to
memory, so the time required to transfer information between the processor and memory
should be such that the processor can operate at, close to, its maximum speed.
Unfortunately, memories that operate at speeds comparable to processors speed are very
costly. It is not feasible to employ a single memory using just one type of technology.
Instead the stored information is distributed in complex fashion over a variety of different
memory units with very different physical characteristics.
The memory components of a computer can be subdivided into three main groups:
1) Internal processor memory: This usually comprises of a small set of high speed
registers used as working registers for temporary storage of instructions and data.
2) Main memory: This is a relatively large fast memory used for program and data
storage during computer operation. It is characterized by the fact that location in the main

memory can be directly accessed by the CPU instruction set. The principal technologies
used for main memory are semiconductor integrated circuits and ferrite cores.
3) Secondary memory: This is generally much larger in capacity but also much slower
than main memory. It is used for storing system programs and large data files and the
likes which are not continually required by the CPU; it also serves as an overflow
memory when the capacity of the main memory is exceeded. Information in secondary
storage is usually accessed directly via special programs that first transfer the required
information to main memory. Representative technologies used for secondary memory
are magnetic disks and tapes.
3.2 Memory device characteristics
The computer architect is faced with a bewildering variety of memory devices to
use. However; all memories are based on a relatively small number of physical
phenomena and employ relatively few organizational principles. The characteristics and
the underlying physical principles of some specific representative technologies are also
discussed.
3.2.1 Cost
The cost of a memory unit is almost meaningfully measured by the purchase or
lease price to the user of the complete unit. The price should include not only the cost of
the information storage cells themselves but also the cost of the peripheral equipment or
access circuitry essential to the operation of the memory.
3.2.2 Access time and access rate
The performance of a memory device is primarily determined by the rate at which
information can be read from or written into memory. A convenient performance measure
is the average time required to read a fixed amount of information from the memory. This
is termed read access time. The write access time is defined similarly; it is typically but
not always equal to the read access time. Access time depends on the physical
characteristics of the storage medium, and also on the type of access mechanism used. It
is usually calculated from the time a read request is received by the memory and to the
time at which all the requested information has been made available at the memory output
terminals. The access rate of the memory is defined is the inverse of the access time.

Clearly low cost and high access rate are desirable memory characteristics;
unfortunately they appear to be largely compatible. Memory units with high access rates
are generally expensive, while low cost memory are relatively slow.
3.2.3 Access mode-random and serial
An important property of a memory device is the order or sequence in which
information can be accessed. If locations may be accessed in any order and the access
time is independent of the location being accessed, the memory is termed as a random
access memory.
Ferrite core memory and semiconductor memory are usually of this type.
Memories where storage locations can be accessed only in a certain predetermined
sequence are called serial access memories. Magnetic tape units and magnetic bubble
memories employ serial access methods.
In a random access memory each storage location can be accessed independently
of the other locations. There is, in effect, a separate access mechanism, or read-write, for
every location. In serial memories, on the other hand, the access mechanism is shared
among different locations. It must be assigned to different locations at different times.
This is accomplished by moving the stored information, the read write head or both.
Many serial access memories operate by continually moving the storage locations around
a closed path or track. A particular location can be accessed only when it passes the fixed
read write head; thus the time required to access a particular location depends on the
relative location of the read/write head when the access request is received.
Since every location has its own addressing mechanism, random access memory
tends to be more costly than the serial type. In serial type memory, however the time
required bringing the desired location into correspondence with a read/write head
increases the effective access time, so access tends to be slower than the random access.
Thus the access mode employed contributes significantly to the inverse relation between
cost and access time.
Some memory devices such as magnetic disks and DRAMs contain large number
of independently rotating tracks. If each track has its own read-write head, the track may
be accessed randomly, although access within track in serial. In such cases the access

mode is sometimes called semi random or direct access. It should be noted that the access
is a function of the memory technology used.
3.2.4 Alterability-ROMS
The method used to write information into a memory may be irreversible, in that
once the information has been written, it cannot be altered while the memory is in use,
i.e., online. Punching holes in cards and printing on paper are examples of essentially
permanent storage techniques. Memories whose contents cannot be altered online are
called read only memories. A ROM is therefore a non-alterable storage device. ROMs are
widely used for storing control programs such as micro programs. ROMs whose contents
can be changed are called programmable read only memories (PROMs).
Memories in which reading or writing can be done with impunity online are
sometimes called read-write memories (RWMs) to contrast them with ROMs. All
memories used for temporary storage are RWMs.
3.2.5 Permanence of storage
The physical processes involved in storage are sometimes inherently unstable, so
that the stored information may be lost over a period of time unless appropriate action is
taken. There are important memory characteristics that can destroy information:
1. Destructive read out
2. Dynamic volatility
3. Volatility
Ferrite core memories have the property that the method of reading the memory
alters, i.e., destroys, the stored information; this phenomenon is called destructive read
out (DRO). Memories in which reading does not affect the stored data are said to have
nondestructive readout (NRDO). In DRO memories, each read operation must be
followed by a write operation that restores the original state of the memory. This
restoration is usually carried out by automatically using a buffer register.
Certain memory devices have the property that a stored 1 tends to become a 0, or
vice versa, due to some physical decay processes. Over a period of time, a stored charge
tends to leak away, causing a loss of information unless the stored charge is restored. This

process of restoring is called refreshing. Memories which require periodic refreshing are
called dynamic memories, as opposed to static memories, which require no refreshing.
Most memories that using magnetic storage techniques are static. Refreshing in dynamic
memories can be carried out in the same way data is restored in a DRO memory. The
contents of every location are transferred systematically to a buffer register and then
returned, in suitably amplified form, to their original locations.
Another physical process that can destroy the contents of a memory is the failure
of power supply. A memory is said to be volatile if the stored information can be
destroyed by a power failure. Most semiconductor memories are volatile, while most
magnetic memories are non-volatile.
3.2.6 Cycle time and data transfer rate
The access time of a memory is defined as the time between the receipt of a read
request and the delivery of the requested information to its external output terminals. In
DRO and dynamic memories, it may not be possible to initiate another memory access
until a restore or refresh operation has been carried out. This means that the minimum
time that must elapse between the initiations of two different accesses by the memory can
be greater than the access time: this rather loosely defined time is called the cycle time of
the memory.
It is generally convenient to assume the cycle time as the time needed to complete
any read or write operation in the memory. Hence the maximum amount of information
that can be transferred to or from the memory every second is the reciprocal of cycle
time. This quantity is called the data transfer rate or band width.

CHAPTER 4
EMERGING MEMORY TECHNOLOGIES
Many new memory technologies were introduced when it is understood that
semiconductor memory technology has to be replaced, or updated by its successor since
scaling with semiconductor memory reached its material limit. These memory
technologies are referred as „Next Generation Memories”. Next Generation Memories
satisfy all of the good attributes of memory. The most important one among them is their
ability to support expansion in three-dimensional spaces. Intel, the biggest maker of
computer processors, is also the largest maker of flash-memory chips is trying to combine
the processing features and space requirements feature and several next generation
memories are being studied in this perspective. They include MRAM, FeRAM, Polymer
Memory Ovonic Unified Memory, ETOX-4BPC, NRAM etc. One or two of them will
become the mainstream.
4.1 Fundamental ideas of emerging memories
The fundamental idea of all these technologies is the bistable nature possible for
of the selected material. FeRAM works on the basis of the bistable nature of the center
atom of selected crystalline material. A voltage is applied upon the crystal, which in turn
polarizes the internal dipoles up or down. i.e. actually the difference between these states
is the difference in conductivity. Non –Linear FeRAM read capacitor, i.e., the crystal unit
placed in between two electrodes will remain in the direction polarized (state) by the
applied electric field until another field capable of polarizing the crystal‟s central atom to
another state is applied.
In the case of Polymer memory data stored by changing the polarization of the
polymer between metal lines (electrodes). To activate this cell structure, a voltage is
applied between the top and bottom electrodes, modifying the organic material. Different
voltage polarities are used to write and read the cells. Application of an electric field to a
cell lowers the polymer‟s resistance, thus increasing its ability to conduct current; the
polymer maintains its state until a field of opposite polarity is applied to raise its
resistance back to its original level. The different conductivity states represent bits of
information.

In the case of NRAM ONO stacks are used to store charges at specific locations.
This requires a charge pump for producing the charges required for writing into the
memory cell. Here charge is stored at the ON junctions.
Phase change memory also called Ovonic Unified Memory (OUM), is based on
rapid reversible phase change effect in materials under the influence of electric current
pulses. The OUM uses the reversible structural phase-change in thin-film material (e.g.,
chalcogenide) as the data storage mechanism. The small volume of active media acts as a
programmable resistor between a high and low resistance with > 40X dynamic range.
Ones and zeros are represented by crystalline versus amorphous phase states of active
material. Phase states are programmed by the application of a current pulse through a
MOSFET, which drives the memory cell into a high or low resistance state, depending on
current magnitude. Measuring resistance changes in the cell performs the function of
reading data. OUM cells can be programmed to intermediate resistance values; e.g., for
multistate data storage.
MRAMs are based on the magneto resistive effects in magnetic materials and
structures that exhibit a resistance change when an external magnetic field is applied. In
the MRAM, data are stored by applying magnetic fields that cause magnetic materials to
be magnetized into one of two possible magnetic states. Measuring resistance changes in
the cell compared to a reference performs reading data. Passing currents nearby or
through the magnetic structure creates the magnetic fields applied to each cell.

CHAPTER 5
OVONIC UNIFIED MEMORY (OUM)
TECHNOLOGY
Among the above-mentioned non-volatile memories, Ovonic Unified Memory is
the most promising one. “Ovonic Unified Memory” is the registered name for the non-
volatile memory based on the material called chalcogenide.
The term “chalcogen” refers to the Group VI elements of the periodic table.
“Chalcogenide” refers to alloys containing at least one of these elements such as the alloy
of germanium, antimony, and tellurium discussed here. Energy Conversion Devices, Inc.
has used this particular alloy to develop a phase-change memory technology used in
commercially available rewriteable CD and DVD disks. This phase change technology
uses a thermally activated, rapid, reversible change in the structure of the alloy to store
data. Since the binary information is represented by two different phases of the material it
is inherently non-volatile, requiring no energy to keep the material in either of its two
stable structural states.
The two structural states of the chalcogenide alloy, as shown in Figure 5.1, are an
amorphous state and a polycrystalline state. Relative to the amorphous state, the
polycrystalline state shows a dramatic increase in free electron density, similar to a metal.
This difference in free electron density gives rise to a difference in reflectivity and
resistivity. In the case of the re-writeable CD and DVD disk technology, a laser is used to
heat the material to change states. Directing a low-power laser at the material and
detecting the difference in reflectivity between the two phases read the state of the
memory.
FIGURE 5.1 Structural states of chalcogenide alloy

Ovonyx, Inc., under license from Energy Conversion Devices, Inc., is working
with several commercial partners to develop a solid-state non-volatile memory
technology using the chalcogenide phase change material. To implement a memory the
device is incorporated as a two terminal resistor element with standard CMOS processing.
Resistive heating is used to change the phase of the chalcogenide material. Depending
upon the temperature profile applied, the material is either melted by taking it above the
melting temperature (Tm) to form the amorphous state, or crystallized by holding it at a
lower temperature (Tx) for a slightly longer period of time, as shown in Figure 5.2. The
time needed to program either state is = 400ns. Multiple resistance states between these
two extremes have been demonstrated, enabling multi-bit storage per memory cell.
However, current development activities are focused on single-bit applications. Once
programmed, the memory state of the cell is determined by reading its resistance.
FIGURE 5.2 Temperature profile
A radiation hardened semiconductor technology incorporating chalcogenide based
memory elements will address both critical and enabling space system needs, including
standalone memory modules and embedded cores for microprocessors and ASICs.
Previously, BAE SYSTEMS and Ovonyx have reported on the results of discrete memory
elements fabricated in BAE SYSTEMS‟ Manassas, Virginia facility. These devices were
manufactured using standard semiconductor process equipment to sputter and etch the
chalcogenide material. While built in the same line used to fabricate radiation-hardened

CMOS products, these memory elements were not yet integrated with transistors. They
were discrete two-terminal programmable resistors, requiring approximately 0.6 mA to
set the device into a low resistance state, and 1.3 mA to reset it to the high resistance
state. One billion (1E9) write cycles between these two states were demonstrated.
Reading the state of the device is non-destructive and has no impact on device wear out
(unlimited read cycles).
5.1 OUM Attributes
 Non-volatile in nature.
 High density ensures large storage of data within a small area.
 Non-destructive read:-ensures that the data is not corrupted during a read cycle.
 Uses very low voltage and power from a single source.
 Write/erase cycles of 10e12 are demonstrated.
 Poly crystalline.
 This technology offers the potential of easy addition of non-volatile memory to a
standard CMOS process.
 This is a highly scalable memory.
 Low cost implementation is expected.
5.2 OUM Architecture
FIGURE 5.3 OUM Architecture

A memory cell consists of a top electrode, a layer of the chalcogenide, and a
resistive heating element. The base of the heater is connected to a diode. As with MRAM,
reading the micrometer-sized cell is done by measuring its resistance. But unlike MRAM
the resistance change is very large-more than a factor of 100. Thermal insulators are also
attached to the memory structure in order to avoid data lose due to destruction of material
at high temperatures.
To write data into the cell, the chalcogenide is heated past its melting point and
then rapidly cooled to make it amorphous. To make it crystalline, it is heated to just
below its melting point and held there for approximately 50ns, giving the atoms time to
position themselves in their crystal locations.

CHAPTER 6
BASIC DEVICE OPERATION
The basic device operation can be explained from the temperature versus time
graph shown in figure 6.1. During the amorphizing reset pulse, the temperature of the
programmed volume of phase change material exceeds the melting point which
eliminates the poly crystalline order in the material. When the reset pulse is terminated
the device quenches to freeze in the disordered structural state. The quench time is
determined by the thermal environment of the device and the fall time of the pulse. The
crystallizing set pulse is of lower amplitude and of sufficient duration to maintain the
device temperature in the rapid crystallization range for a time sufficient for crystal
growth.
FIGURE 6.1 Temperature v/s time plot
6.1 Technology and performance
The figure 6.2 on next page shows device resistance versus write pulse width. The
reset resistance saturates when the pulse width is long enough to achieve melting of the
phase change material. The set pulse adequately crystallizes the bit in 50 ns with a
RESET/SET resistance ratio of greater than 100.

FIGURE 6.2 Resistance v/s pulse width plot
6.2 V-I Characteristics
FIGURE 6.3 V-I Characteristics
The figure 6.3 shows V-I characteristics of the OUM device. At low voltages, the
device exhibits either a low resistance (~1k) or high resistance (>100k), depending on its
programmed state. This is the read region of operation. To program the device, a pulse of
sufficient voltage is applied to drive the device into a high conduction “dynamic on
state”. For a reset device, this requires a voltage greater than Vth.
Vth is the device design parameter and for current memory application is chosen
to be in the range of 0.5 to 0.9 V. to avoid read disturb, the device read region as shown
in the figure, is well below Vth and also below the reset regime.

The device is programmed while it is in the dynamic on state. The final
programmed state of the device is determined by the current amplitude and the pulse
duration in the dynamic on state. The reciprocal slope of the V-I curve in the dynamic on
state is the series device resistance.
6.3 R-I Characteristics
FIGURE 6.4 R-I Characteristics
The figure 6.4 shows the device read resistance resulting from application of the
programming current pulse amplitude. Starting in the set condition, moving from left to
right, the device continues to remain in SET state as the amplitude is increased. Further
increase in the pulse amplitude begins to reset the device with still further increase
resetting the device to a standard amorphous resistance. Beginning again with a device
initially in the RESET state, low amplitude pulses at voltages less than Vth do not set the
device. Once Vth is surpassed, the device switches to the dynamic on state and
programmed resistance is dramatically reduced as crystallization of the material is
achieved. Further increase in programming current further crystallizes the material, which
drops the resistance to a minimum value. As the programming pulse amplitude is
increased further, resetting again is exhibited as in the case above. Devices can be safely
reset above the saturation point for margin. Importantly, the right side of the curve
exhibits direct overwrite capability, where a particular resistance value can be obtained
from a programming pulse, irrespective of the prior state of the material. The slope of the
right side of the curve is the device design parameter and can be adjusted to enable a
multistate memory cell.

CHAPTER 7
INTEGRATION WITH CMOS
Under contract to the Space Vehicles Directorate of the Air Force Research
Laboratory (AFRL), BAE SYSTEMS and Ovonyx began the current program in August
of 2001 to integrate the chalcogenide-based memory element into a radiation-hardened
CMOS process. The initial goal of this effort was to develop the processes necessary to
connect the memory element to CMOS transistors and metal wiring, without degrading
the operation of either the memory elements or the transistors. It also was desired to
maximize the potential memory density of the technology by placing the memory element
directly above the transistors and below the first level of metal as shown in a simplified
diagram in Figure 7.1.
FIGURE 7.1 Integration with CMOS
To accomplish this process integration task, it was necessary to design a test chip
with appropriate structures. This vehicle was called the Access Device Test Chip (ADTC)
since each memory cell requires an access device (transistor) in addition to the

chalcogenide memory element. Such a memory cell, comprised of one access transistor
and one chalcogenide resistor, is herein referred to as a1T1R cell. The ADTC included
272 macros, each with 2 columns of 10 probe pads. Of these, 163 macros were borrowed
from existing BAE SYSTEMS‟ test structures and used to verify normal transistor
operation. There were 109 new macros designed to address the memory element features.
These included sheet resistance and contact resistance measurement structures, discrete
memory elements of various sizes and configurations, and two 16-bit 1T1R memory
arrays.
Short loop (partial flow) experiments were processed using subsets of the full
ADTC mask set. These experiments were used to optimize the process steps used to
connect the bottom electrode of the memory element to underlying tungsten studs and to
connect an additional tungsten stud level between Metal 1 and the top electrode of the
memory element. A full flow experiment was then processed to demonstrate integrated
transistors and memory elements.
FIGURE 7.2 V-I Characteristics
Figure 7.2 shows the V-I characteristic for a 1T1R memory cell successfully
fabricated using the ADTC vehicle. The voltage is applied to one of the two terminals of
the chalcogenide resistor, and the access transistor (biased on) is between the other
resistor terminal and ground. The high resistance amorphous material shows very little
current below a threshold voltage (VT) of 1.2V. In this same region the low resistance
polycrystalline material shows a significantly higher current. The state of the memory cell

is read using the difference in V-I characteristics below VT. Above VT, both materials
display identical V-I characteristics, with a dynamic resistance (RDYNAMIC) of ~1k. In
itself, this transition to a low resistance electrical state does not change the structural
phase of the material. However, it does allow for heating of the material to program it to
the low resistance state (1) or the high resistance state (0). Extrapolation of the portion of
the V-I curve that is above VT to the X-axis yields a point referred to as a holding voltage
(VH). The applied voltage must be reduced below VH to exit the programming mode.
FIGURE 7.3 R-I Characteristics
Figure 7.3 shows the operation of a 1T1R memory, again with the access
transistor biased on. The plotted resistance values were measured below VT, while the
current used to program these resistances was measured above VT. Similar to the
previously demonstrated stand-alone memory elements, these devices require
approximately 0.6 mA to set to the low resistance state (R SET) and 1.2 mA to reset to
the high resistance state (R RESET). The circuit was verified to be electrically open with
the access transistor biased off.

FIGURE 7.4 Drain current v/s gate voltage plot
Figure 7.4 shows the total dose (X-ray) response of N-channel transistors
processed through the chalcogenide memory flow. The small threshold voltage shift is
typical of BAE SYSTEMS‟ standard radiation-hardened transistor processing. All other
measured parameters (drive current, threshold voltage, electrical channel length, contact
resistance, etc.) were also typical of product manufactured without the memory element.

CHAPTER 8
ADVANTAGES AND RISK FACTORS OF OUM
Advantages
 OUM uses a reversible structural phase change.
 Small active storage medium.
 Simple manufacturing process.
 Simple planar device structure.
 Low voltage single supply.
 Reduced assembly and test costs.
 Highly scalable- performance improves with scaling.
 Multistate are demonstrated.
 High temperature resistance.
 Easy integration with CMOS.
 It makes no effect on measured CMOS transistor parametric.
 Total dose response of the base technology is not affected.
Risk factors
 Reset current < min W switch current.
 Standard CMOS process integration.
 Alloy optimization for robust high temp operation and speed.
 Cycle life endurance consistency.
 Endurance testing to 10 – DRAM.
 Defect density and failure mechanisms.

CHAPTER 9
ABOUT CHALCOGENIDE ALLOY
Chalcogenide or phase change alloys is a ternary system of Gallium, Antimony
and Tellurium. Chemically it is Ge2Sb2Te5.
FIGURE 9.1 Ternary system
Production Process: Powders for the phase change targets are produced by state-
of –the art alloying through melting of the raw material and subsequent milling. This
achieves the defined particle size distribution. Then powders are processed to discs
through Hot Isotactic Pressing.
9.1 Comparison of amorphous and crystalline state
Amorphous Crystalline
Short range atomic order. Long range atomic order.
Low free electron density. High free electron density.
High activation energy. Low activation energy.
High resistivity. Low resistivity.
9.2 Test results
Test results confirmed that the insertion of a chalcogenide manufacturing flow had
no effect on measured CMOS transistor parametric and did not change the total dose
response of the base technology. Preliminary results on send-ahead package departs
indicate full functionality of the 64 Kbit memory arrays. Further characterization of the
ADTC wafers and packaged devices from the CTCV wafers will include chalcogenide

material-specific studies, such as write cycle endurance (a.k.a. “cycle life”), operating and
storage temperature effects and further radiation effects tests on packaged parts, to
include total dose (60Co) and heavy ion exposure. Minimum write and read cycle timing,
layout spacing evaluation, data pattern insensitivity and other design related
characterization will be conducted to support product optimization.
Companies working with Ovonic Unified Memory have their ultimate goal to
gather enough data to begin a product design targeting a 1–4 Mbit C-RAM device that is
latch-up and SEU immune to greater than 120 LET and total dose hard to greater than 1
Mrad (Si), operating across the full temperature range commonly specified for space
applications.

CONCLUSION
Unlike conventional flash memory Ovonic unified memory can be randomly
addressed. OUM cell can be written 10 trillion times when compared with conventional
flash memory. The computers using OUM would not be subjected to critical data loss
when the system hangs up or when power is abruptly lost as are present day computers
using DRAM a/o SRAM. OUM requires fewer steps in an IC manufacturing process
resulting in reduced cycle times, fewer defects, and greater manufacturing flexibility.
These properties essentially make OUM an ideal commercial memory. Current
commercial technologies do not satisfy the density, radiation tolerance, or endurance
requirements for space applications. OUM technology offers great potential for low
power operation and radiation tolerance, which assures its compatibility in space
applications. OUM has direct applications in all products presently using solid state
memory, including computers, cell phones, graphics-3D rendering, GPS, video
conferencing, multi-media, Internet networking and interfacing, digital TV, telecom,
PDA, digital voice recorders, modems, DVD, networking (ATM), Ethernet, and pagers.
OUM offers a way to realize full system-on-a-chip capability through integrating unified
memory, linear, and logic on the same silicon chip.
Non-volatile OUM with fast read and write speeds, high endurance, low
voltage/low energy operation, ease of integration and competitive cost structure is
suitable for ultra-high density, stand alone and embedded memory applications. These
attributes make OUM an attractive alternative to flash memory technology and potentially
competitive with volatile memory technologies.

REFERENCES
Text books
1) OUM - a 180 nm nonvolatile memory cell element technology for standalone and
embedded applications - Stefan Lai and Tyler Lowrey.
2) Current status of the phase change memory and its future (2003) – Stefan Lai.
3) Ovonic unified memory - a high-performance nonvolatile memory technology for
stand-alone memory and embedded applications (0)by M Gill, T Lowrey, J Park.
Website links
1) http://en.wikipedia.org/wiki/Ovonic_Unified_Memory
2) http://ovonicunifiedmemory.blogspot.in/
3) http://www.studentsphere.co/index.php/technical-articles/computers-it/90-tet
4) http://www.techopedia.com/definition/2797/phase-change-memory-pcm
5) http://maltiel-consulting.com/Nonvolatile_Phase_Change_Memory.htm

PHASE CHANGE MEMORY

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