A High-resolution Vernier Gated-Ring-Oscillator TDC                    in 90-nm CMOS                                      ...
Fig.2 Block Diagram of proposed vernier GRO based TDC   The GRO core consists of two 9-stage ring oscillators          ris...
Fig.3 GRO core and sampling/reset delay                                                   Fig.4 Adaptive PFDnext measureme...
multi-clock counter                                         GRO1             PFD                                         G...
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  1. 1. A High-resolution Vernier Gated-Ring-Oscillator TDC in 90-nm CMOS Ping Lu, Pietro Andreani Department of Electrical and Information Technology, Lund University, Sweden Email: {Ping.Lu, Pietro.Andreani }@eit.lth.se Abastract—A Vernier Gate-Ring-Oscillator (GRO) Time to Digital Converter (TDC) is proposed and implemented in 90-nm CMOS process technology. It utilizes two GRO chains as the delay lines. The time resolution is determined by the difference between two delays, so not limited by the process. Moreover, the quantization noise can be first-order shaped by the gated behavior in the oscillators, which further improves the in-band TDC noise contribution for an ADPLL. Operating at 1.2-V supply with 250MHz clock, the chip achieves a less-than-10ps coarse resolution (varies with digital control bits) and consumes only 3.6-mA. INTRODUCTION All Digital Phase-Locked Loop (ADPLL) is now a hot research topic for more flexibility and programmability Fig.1 GRO principle and noise shaping compared with its analog counterpart. In an ADPLL, Digitally Controlled Oscillator (DCO) phase noise and then developed [5]. TDC quantization noise dominate the in-band and Noise shaping is another method for reducing in-band out-band noise respectively. Thus in some ADPLL TDC noise contribution [6]. This type of TDC has still a applications which need a wide bandwidth, the coarse resolution of an inverter delay, but the quantization noise of TDC is important to the total noise corresponding large quantization noise can be first-order performance. shaped. It pushes most of the noise to high-frequency The TDC noise contribution, within the loop bandwidth, region which is then filtered by the loop filter in ADPLLs. at the ADPLL RF output is [1] As shown in Fig.1, the cyclic behavior of GRO helps (2π ) 2 Δtdelay 2 1 reuse the staggered clocks circularly and the enable STDC = ( ) 12 TDCO f REF transistors (NMOS and PMOS) in the delay cell hold the (1) oscillation node state between measurements. At next where Δtdelay denotes the delay time of an delay cell in the measurement interval, the oscillator starting phase TDC chain, TDCO denotes the period of RF output, and fREF corresponds to the stopping phase of the current is frequency of the reference clock. As can be seen, a measurement interval. The variable starting phase smaller Δtdelay leads to a smaller TDC quantization noise. effectively scrambles the quantization noise across the In a traditional TDC where the time resolution provided different measurement intervals and also introduces a by a self-loaded inverter, the quantization noise is limited first-order noise shaping. by a single inverter, so is limited by a process technology. Considering that the coarse resolution in GRO based Some advanced approaches like vernier structure [2], TDC is still limited by an inverter delay, a new TDC pulse shrinking [3] and sub-exponent TDC [4] have combining vernier and GRO structures is proposed in this therefore been proposed to achieve much shorter work. It uses two GROs in a classic vernier TDC to resolvable time than an inverter itself. achieve both process-independent high time resolution and A vernier TDC uses two delay lines with respective first-order shaped noise characteristic. delay of τ 1 and τ 2 instead of a single line. The time This paper is arranged as follows. Section II describes resolution Δtdelay becomes a delay difference τ 1 − τ 2 , not the architecture of the vernier GRO based TDC. The an inverter delay any more. This delay difference can be circuit implementation is detailed in Section III. Section very small (down to 0) theoretically regardless of IV gives the layout and simulation results. Conclusions are thermo-noise of devices. Thus TDC noise contribution can drawn in Section V. be reduced greatly according to (1). Since the time VERNIER GATED-RING-OSCILLATOR TDC resolution is determined by a very small delay difference in the vernier structure, a large number of inverter stages Fig.2 shows the structure of the proposed TDC. It are required to cover a large detection range, incurring includes the GRO core, Phase and Frequency Detector large silicon overhead. A ring-oscillator vernier TDC was (enable generator) and a multi-clock counter.978-1-4244-8971-8/10$26.00 c 2010 IEEE
  2. 2. Fig.2 Block Diagram of proposed vernier GRO based TDC The GRO core consists of two 9-stage ring oscillators rising edges in SGRO will lag their corresponding risingand a sampling block. As in a vernier TDC, the two edges in FGRO after passing a certain amount ofoscillators have different delay cells. The delay of the first staggered phases. Once the lag happens, RBO will resetoscillator cell is a little longer than that of the second one. PFD and the measurement window will be closedThe difference between them indicates the time resolution. immediately (EN_REF/ EN_CKV = ”0”).Use SGRO (slow) and FGRO (fast) to denote those two CIRCUIT DETAILSoscillators. EN_REF and EN_CKV are enable signals forthem respectively. The oscillators work at the enable state A. Gated-Ring-Oscillator core(EN_REF/ EN_CKV=”1”) and hold their states at the Fig.3 shows the detailed GRO core. Two identical ringdisable state (EN_REF/ EN_CKV=”0”). The sampling oscillators are used. Delay difference comes from differentblock reads the phase information of the 9 pairs of control inputs (c<1:15>) to them. EN and ENB are enableone-one correspondence clocks and feeds back a control signals for NMOS and PMOS gate transistors in delaysignal. At initialization, SGRO always leads FGRO and cells. c<1:15> are thermometer-code bits which arethe sampled value RBO is “0”. When any phase in SGRO connected to 15 unit MOS capacitors directly. The delaylags its counterpart phase in FGRO, RBO sends a positive gain is about 1.28ps/bit. For a vernier TDC application,pulse to reset PFD. Then EN_REF and EN_CKV return to the inputs c<1:15> are always different for SGRO and“0” to hold the oscillators’ state. All clock (ck<0:8>) FGRO because a small time difference is needed toedges from SGRO are also used by a multi-clock counter quantize phase error.to calculate the digitized time error in each measurement The GRO delay cell is shown at the top right corner ininterval. Since the gate transistors are used in the GROs, Fig.3. NMOS and PMOS enable transistors are controlledquantization error residue will be accumulated in each by EN and ENB respectively. When both enable transistorsmeasurement. That means a first-order noise shaping is are in the conducting condition, the delay cell works like aachieved at the same time, as shown in Fig.1. traditional inverter. Then the inverter ring oscillates as a It should be noticed that in this work only rising edge of common ring oscillator. However, when EN and ENB cutall oscillator clocks is used for the sampling block to get off the enable transistors, the ring will stop oscillating andrid of rising and falling edge mismatch. It suggests the keep the output nodes’ charge unchanged because nocoarse time resolution is double difference between two current path is connected to power supply or ground anyinverter delays because non-inversion neighboring phases more. The oscillation frequency of each GRO can be tunedare preferred to use. discretely by 15 thermometer-code switches c<1:15>. For Multi-clock counter needs to count at each rising edge SGRO, these 15 switches are always connected to groundof ck<0:8>. The count enable signal is SGRO’s gate suggesting a fixed cell delay (also a fixed frequency).control EN_REF. When EN_REF = ”1”, each rising edge Then the delay difference between SGRO and FGRO aretriggers the accumulator to add “1” to the sum. When determined only by the 15 switches in FGRO. Actually, toEN_REF = ”0” (the measurement is finished), the counter reduce off-chip controls, the 15 thermometer-codesaves the sum into a latch and then resets the accumulator switches are generated by an additionalpreparing for the next measurement. binary-to-thermometer coder. PFD generates two enable signals (EN_REF, EN_CKV) Sampling flip-flops detect the phase error between eachand their reversal signals (ENB_REF, ENB_CKV) to pair of staggered clocks. Once one of those sampled valuecontrol NMOS and PMOS enable transistors in GRO becomes “1” (that is the staggered lagged clocks catch updelay cells. EN_REF/EN_CKV is supposed to be a with those leading ones), RBO becomes “1” to reset PFD.rectangular signal suggesting the phase error information The key point for GRO core is the absolute delay inbetween input clocks REF and CKV. When REF rising each oscillator. When phase ck<0(n+1)> catches up withedge arrives first, for example, EN_REF becomes “1” phase ck<n+1>, as illustrated in lower right of Fig.3,(ENB_REF becomes “0”) forcing SGRO to start o<n+1> needs transmission time to become “1”. Theoscillating first. When CKV rising edge arrives after a situation for RBO and EN_REF/EN_CKV is the same. Duewhile, EN_CKV also becomes “1” forcing FGRO to work. to this kind of gate delay, two GROs keep oscillating for aIn this example, EN_REF leads EN_CKV. It means that short while after ck<n+1> is already lagged. The criticalthe first rising edge in SGRO leads the first rising edge in feedback path has a typical delay of 100ps~200psFGRO during the measurement interval. If these two (obtained by post layout simulation). No more rising edgesoscillators have the same frequency, the phase error will are supposed to be generated during this additional timebe always kept. However, due to the delay difference, the interval, otherwise wrong sampling may happen in the
  3. 3. Fig.3 GRO core and sampling/reset delay Fig.4 Adaptive PFDnext measurement. That means the absolute delay of eachvernier line (two-inverter delay) should be longer than200ps. Here 400ps is adopted for some margin.B. Phase & frequency detector (PFD) In the GRO core, the SRGO (driven by EN_REF) celldelay is always longer than FGRO (driven by EN_CKV)cell delay. It requires EN_REF to lead EN_CKV always.However for a normal PFD in which EN_REF/EN_CKV iscorresponding to REF/CKV, this precondition cannot beguaranteed because CKV frequency and phase are adjusteddynamically in ADPLLs. A SR-latch is therefore used asan arbiter, as shown in Fig.4. It senses the leading edgebetween REF and CKV and gives a sign signal which Fig.5 Multi-clock countercontrols four multiplexers. When REF is leading, sign is“0” meaning EN_REF corresponds to REF. On the clock frequency and hardware consumption. In each group,contrary, EN_REF corresponds to CKV. clocks should have a large interval between rising edges,C. Multi-clock counter which eases the strain of accumulator. The two-inverter The digitized phase error can be calculated using delay is about 400ps in this work. To make the countermultiple clocks ck<0:8> from SGRO in each measurement work with a large margin, the nine clocks are grouped intointerval. One approach is to assign one individual 5 groups with each containing two. The two clocks withaccumulator for each clock, which consumes more adders the longest rising interval (e.g. ck<0> and ck<8>) shareand flip-flops. If all clocks could be combined to one that one accumulator. Each clock rising edge produces acontains all edges, only one accumulator is enough. But narrow pulse by inserting a delay in the reversion-inputthe new clock frequency is inevitably very high bearing on path of the first NAND gate, as shown in Fig.5. Then thethe accumulator speed. To tackle the above problem, we second NAND gate combines these two positive pulses topropose to group those clocks to get a tradeoff between one to clock an accumulator. The sum of each accumulator
  4. 4. multi-clock counter GRO1 PFD GRO2 (a) dummy load Fig.6 Layout of TDC (b) Fig.8 Simulated transistor-level TDC output (a) (b) (a) Bit stream (coded decimal) (b) FFT analysis Fig.7 Simulated PSD of TDC output in Simulink (a) Proposed TDC (b) Classic vernier TDC quantization noise due to coarse resolution is well first-order shaped (see Fig.8(b)).should be synchronized and then added together. Theabove operation runs only in the measurement interval CONCLUSIONS(EN_REF = ”1”). This paper describes a Vernier-GRO TDC which uses LAYOUT AND SIMULATION vernier principle to get a high time resolution and GRO’s to achieve first-order shaped quantization noise. The The above presented TDC has been implemented using first-order noise shaping pushes much noise to the90-nm CMOS technology. Fig.6 shows the layout of the high-frequency region which can be filtered by a low-passproposed TDC (without I/O pads). The active area is noise transfer function in an ADPLL. The chip is0.18mm*0.15mm. The multi-clock counter uses staggered implemented in 90-nm CMOS technology and occupiesclocks from SGRO as referred above. Since FGRO has no 0.18mm*0.15mm area.identical load capacitances as SGRO, some dummy gateloads are used to compensate delay mismatch. REFERENCES We compare the proposed TDC and the classic vernier [1] R. B. Staszewski and P. T. Balsaras, “All-Digital FrequencyTDC in Fig.7 by simulating in a simulink platform. Synthesizer in Deep-Submicron CMOS”, John Wiley & Sons,Sinusoidal delay is used as error input. These two TDCs 2006has the same Δtdelay = 6.4 ps . For a classic vernier TDC, [2] P. Dudek, S.Szczepanski and J.V. Hatfield, “A High-Resolution CMOS Time-to-Digital Converter Utilizing athe quantization noise has a “white” noise floor. However Vernier Delay Line”, IEEE Journal of Solid-State Circuits,in the proposed TDC, most of the quantization noise is vol.35 No. 2, Feb. 2000, pp. 240-247.pushed to high-frequency region (first-order shaped). A [3] Y. Liu, U. Vollenbruch, Y.J. Chen, etc., “A 6ps Resolution250MHz sampling clock is used in this example. Noise Pulse Shrinking Time-to-Digital Converter as Phase Detector inperformance below 20MHz can be well improved, as seen Multi-Mode Transceiver”, IEEE radio and wireless symposium,in the fig.7 (a). pp. 163-166, 2008 Fig.9 shows the transistor-level simulation of TDC [4] S.K. Lee, Y.H. Suh, H.J. Park, J.Y. Sim, “A 1GH ADPLL with a 1.25ps Minimum-Resolution Sub-Exponent in 0.18umoutput bit stream and its FFT analysis. A dc-delay of 22ps CMOS”, in 2010 IEEE Int. Solid-State Circuits Conf. Dig. Tech.is used as input error. If ΔT denotes the input time error Papers, pp.482-483between REF and CKV, the digitized error should be equal [5] H.H. Chang, P.Y. Wang, J.H. Zhan, etc, “A Fractionalto ΔT / Δtdelay . Δtdelay = 6.4 ps (5 unit capacitor controls Spur-Free ADPLL with Loop-Gain Calibration and Phase-Noise Cancellation for GSM/GPRS/EDGE”, in 2008 IEEE Int.are set to “1”) is set in the simulation. For a regular vernier Solid-State Circuits Conf. Dig. Tech. Papers, pp.200-201TDC, it should give a result of 3 by simply truncating the [6] Chun-Ming Hsu, Matthew Z. Straayer and Michael H. Perrott,fractional error. But for this TDC, the output varies “A Low-Noise Wide-BW 3.6GHz Digital Δ∑ Fractional-Nbetween 3 and 4 with an average value of 3.41 (see Fig.8 Frequency Synthesizer With a Noise-Shaping Time-to-Digital( a) ) . T h i s s h o ws a n o t h e r b e n e f i t o f a c c ur a c y Converter and Quantization Noise Cancellation”, IEEE Journaloverwhelming the classic vernier TDCs. Moreover, of Solid-State Circuits, vol. No. Dec. 2008, pp. 2776-2786