CHANNELIZER FOR SOFTWARE
DEFINED RADIO USING VLSI
Objective Proposed design of our
Basic architecture of channelizer
channelizer Architecture of our design
CIC filter Simulation results
Fast Fourier transform Synthesis results
What is software defined radio Conclusion
Field programmable gate array Reference
The objective of our project is to design a power efficient
channelizer for software defined radio.
We have proposed a model of increased stage CIC filter
and FFT for channelizer.
For designing model sim altera is used for simulation
purpose and xilinz ISE is used for synthesis.
Basic architecture of channelizer
Integrator Decimator 8 point FFT
CIC FILTER BLOCK
Used to achieve arbitrary and large sample rate changes in
Used as decimation or interpolation filters.
Efficiently implemented without multipliers, utilizing only
adders and subtractors.
Single CIC filter block diagram
+ + R + +
integrator decimator comb filter
1-32-bit input data width.
1-8 cascaded stages.
1-4 cycles differential delay.
Run-time programmable for both decimation and
2-16,384 decimation and interpolation sampling rate
Multi-channel (up to 4 channels) support for both
decimation and interpolation.
Fully synchronous, single-clock design.
An integrator is a single-pole IIR filter .
with a unity feedback coefficient.
operating at a higher sampling rate, fS.
A comb is a FIR filter .
with M unity differential delays .
operating at a lower sampling rate.
Fast Fourier transform
An efficient algorithm to compute the discrete Fourier
transform (DFT) and its inverse.
An FFT computes the DFT and produces exactly the
same result as evaluating the DFT.
Difference is that an FFT is much faster.
DFT of N points takes O(N 2) arithmetical operations,
FFT take only O(N log N) operations.
What is Software Defined
A collection of hardware and software technologies.
Radio in which some or all of the physical layer functions
are software defined.
Radio’s operating functions are implemented through
modifiable software or firmware .
Operating on programmable processing technologies.
Benefits of SDR
For Radio Equipment Manufacturers and System
For Radio Service Providers.
For End Users - from business travelers to soldiers on the
Field programmable gate array
An integrated circuit designed to be configured by the
customer or designer after manufacturing.
Configuration is generally specified using a hardware
description language (HDL).
Contain programmable logic components called "logic
Hierarchy of reconfigurable interconnects that allow the
blocks to be "wired together“.
FPGA design and programming
The HDL form is suited to work with large structures .
It's possible to just specify numerically rather than having
to draw every piece by hand.
Electronic design automation tool is used and technology-
mapped netlist is generated.
The netlist can then be fitted to the actual FPGA
architecture using a process called place-and-route.
The user will validate the map, place and route results
Once the design and validation process is complete
The binary file generated is used to reconfigure the FPGA.
Proposed design of
5 stage integrator and 5 stage comb filter with one
To increase efficiency totally there are 8 complete stages
An 8 point FFT block.
Architecture of our design
xin x0 out0
Stage 3 x2 x1 out2
8 point FFT
CIC FILTER BLOCK
Individual CIC filter of our
I1 I2 I3 I4 I5 R C1 C2 C3 C4 C5
I1,I2,I3,I4,I5 are integrator
R is decimator
C1,C2,C3,C4,C5 are comb filter
Sample coding of integrator
For integrator section
always @(posedge clk)
Efficiency in terms of architecture optimizations such as
those made in the Polyphase FFT.
Implementation aspects leading to smaller area, low
power, radiation hardness and low cost seem very
The designed channelizer can be utilized in real time SDR
There is promising decrease in noise by the design.
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Prentice Hall, 1981.
2. Package”, GOMAC 2002 Digest of Papers.
3. A.M. Badda and M. Donati, “The Software Defined Radio
Technique Applied to the RF Front-End for Cellular Mobile
Systems”, in Software Radio Technologies and Services”,
Editor Enrico Del Re, Springer-Verlog 2001.
4. P.P Vaidyanathan, “Multirate Digital Filters, Filter Banks,
Polyphase Networks and Applications: A Tutorial”, Proc.
IEEE, Vol. 78, pp 56-93, 1990
5. K.Roy, et. al., “Hardware Architecture and VLSI
Implementation of a Low-Power High-Performance Polyphase
Channelizer with Applications to Subband Adaptive Filtering”,
IEEE International Conference on Acoustics, Speech, and
Signal Processing 2004.
6. K. Roy, et al., “CSDC: a new complexity reduction
technique for parallel multiplierless implementation of digital
FIR filters”, submitted to IEEE Trans. Circuits and Systems II:
Analog and Digital Signal Processing.
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John Wiley & Sons, Inc., ISBN 0-471-11488-X, 2000.
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A General-purpose Module for Sensor Integration”, Military
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Reconfigurable Processors in a 3-
Dimensional C. Poivey, “Radiation Hardness Assurance for
Space Systems,” IEEE NSREC2002 short course,Section V,
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Commercially Available 1M/4Mbit for Space Applications,”
IEEE NSREC 1998 data workshop proceedings, 1998.