The document provides a series of questions and answers on UVM (Universal Verification Methodology) concepts, including methods to start simulations, connect components, and roles of various UVM components like uvm_scoreboard and uvm_sequence. Key functions such as run_test() for running simulations and the significance of uvm_config_db for configuration management are also discussed. Additionally, it explains the differentiation between active and passive agents, factory registration, and methods to control sequences within UVM testbenches.

1. 86) What method is called to run the main
simulation in UVM?
A. run_test
B. run
C. start_test
D. main
Ans:
run_test
• In UVM, to start the main
simulation, you use the run_test()
function. This function starts
everything in the UVM environment,
including test components, stimulus
generation, and checks. You can
either let it run the default test or
specify a test name to run.
initial begin
run_test(); // Starts the simulation
end

2. 87) In UVM , which of the following correctly
establishes a connection between port - to - ports?
A. subcomponent.port.connect(port);
B. port.connect(subcomponent.port);
C. subcomponent.port => port;
D. subcomponent.port = port;
Ans:
subcomponent.port.connect(port);
• This is the correct syntax for
connecting ports in UVM. The
connect() method is used to bind
one port (from a subcomponent) to
another, ensuring that data or
transactions can flow between them.
• Here, the port of the subcomponent
is connected to another port. This is
commonly used in the
connect_phase() of UVM
components.

3. 88) Which UVM component checks functional
correctness of DUT outputs?
A. check
B. uvm_scoreboard
C. uvm_coverage_collector
D. uvm_config_db
Ans:
uvm_scoreboard
• The uvm_scoreboard is
responsible for comparing
expected outputs with the actual
outputs from the DUT. It
typically receives transactions
from monitors and performs
checks to verify that the DUT is
behaving correctly.

4. 89) Which phase is responsible for stimulus
generation in UVM?
A. build_phase
B. run_phase
C. reset_phase
D. cleanup_phase
Ans:
run_phase
• The run_phase is where the
actual simulation and stimulus
generation occur. This phase is
time-consuming and is where the
stimulus is driven to the DUT,
typically by the driver, and
responses are collected. It runs
concurrently with the simulation
and handles the execution of
sequences and transactions.

5. 90) What is the significance of uvm_config_db in
UVM?
A. To provide a database for storing
simulation results
B. To store configurations for UVM
components
C. To manage command-line arguments
D. To handle factory registration
Ans:
To store configurations for UVM
components.
• The uvm_config_db is used to
store and retrieve configuration
settings for UVM components. It
allows passing of configuration
parameters and objects between
different parts of the UVM
testbench without needing direct
connections, making the
testbench more modular and
flexible.

6. 91) What is the function of the uvm_sequence class
in UVM?
A. To represent a series of transactions
sent to the DUT
B. To model a specific type of stimulus
C. To define the environment for the
verification
D. To collect coverage data
Ans:
To represent a series of transactions
sent to the DUT.
• The uvm_sequence class is used
to define a sequence of
transactions or stimuli that will
be generated and sent to the
Design Under Test (DUT)
through a sequencer and driver.
Sequences are used to control the
flow of data and transactions
during simulation, making it
easier to create complex test
scenarios.

7. 92) In UVM, what is the primary purpose of the
uvm_phase class?
A. To define different phases of
simulation
B. To manage data flow between
components
C. To provide a mechanism for random
generation
D. To handle timing constraints
Ans:
To define different phases of simulation
• The uvm_phase class is
responsible for managing and
coordinating the different phases
of a UVM simulation, such as
build, connect, run, and
shutdown phases. These phases
ensure that various components
in the UVM testbench execute
their tasks in the correct order
during simulation.

8. 93) In UVM, the new() method is used to create an object
instance. How does the create() method in UVM differ
from new()?
A. create() method is identical to new() but is not
part of the UVM library.
B. create() allows the UVM factory to return an
object, enabling factory overrides, while new()
directly instantiates a class.
C. create() only works for primitive data types, while
new() is for class objects.
D. create() is used only in SystemVerilog without
UVM.
Ans:
create() allows the UVM factory to return an
object, enabling factory overrides, while new()
directly instantiates a class.
• new(): Directly creates an
instance of a class, bypassing the
UVM factory.
• create(): Uses the UVM factory to
create an instance of a class,
allowing the factory to apply any
overrides if necessary. This is
essential for enabling flexible
testbench setups and object
substitution without modifying
the testbench code.

9. 94) In UVM, what is the difference between an active
agent and a passive agent?
A. An active agent only monitors signals,
while a passive agent drives signals to the
DUT.
B. A passive agent instantiates both the
driver and sequencer, while an active agent
does not instantiate them.
C. An active agent drives signals to the DUT
and monitors the interface, while a passive
agent only monitors signals without
instantiating the driver or sequencer.
D. Both active and passive agents perform
the same actions, but the passive agent uses
fewer resources.
• Active agent: Contains both a driver (which
drives signals to the DUT) and a monitor (which
observes the DUT's behavior). It also typically
includes a sequencer to generate stimulus.
• Passive agent: Only includes a monitor to
observe and check signals but does not have a
driver or sequencer to generate or drive stimulus
to the DUT.
Ans:
An active agent drives signals to the DUT and
monitors the interface, while a passive agent
only monitors signals without instantiating the
driver or sequencer.

10. 95)In UVM, how can a sequence be started?
A. By only calling the start()
method.
B. By using the uvm_run() method
or the macro uvm_start.
C. By calling the start() method or
using the macro uvm_do.
D. By instantiating the sequence
directly within the driver.
• The start() method is used to
explicitly start a sequence on a
sequencer, while the uvm_do macro
simplifies sequence execution by
abstracting away some of the details
like sequence item creation and
starting.
Ans:
By calling the start() method or
using the macro uvm_do.

11. 96) In UVM, what is the correct syntax for creating a
component and an object, respectively?
A. <instance_name> =
<type>::<type_id>::create("<name>", <parent>) for
components and <instance_name> =
<type>::<type_id>::create("<name>", <parent>) for
objects.
B. <instance_name> =
<type>::<type_id>::create("<name>", <parent>) for
components and <instance_name> =
<type>::<type_id>::create("<name>") for objects.
C. <instance_name> = <type>::create("<name>",
<parent>) for both components and objects.
D. <instance_name> =
<type>::<type_id>::create("<name>") for
components and <instance_name> =
<type>::<type_id>::create("<name>", <parent>) for
objects.
• In UVM, components require both a name and
a parent component because they are
hierarchical and need to be placed within the
testbench structure. Objects, on the other
hand, are not hierarchical, so only the name is
required when creating them.
Ans:
<instance_name> =
<type>::<type_id>::create("<name>",
<parent>) for components and
<instance_name> =
<type>::<type_id>::create("<name>") for
objects.

12. 97) Why is factory registration important in a UVM-
based testbench, even though the new() function can
be used to create class objects?
A. It simplifies the creation of objects but does not
allow any object overriding.
B. Factory registration allows the UVM factory to
override an object of one type with its derived type
without modifying the testbench structure.
C. It ensures that objects are only created at the
beginning of the simulation.
D. The new() function is not valid for creating
objects in a UVM testbench.
Ans:
Factory registration allows the UVM factory to
override an object of one type with its derived
type without modifying the testbench structure.
• A. While factory registration
simplifies object creation, it also
allows for object overriding.
• C. This is not strictly true. Objects
can be created throughout the
simulation using the factory.
• D. This is incorrect. The new()
function is valid for creating
objects in UVM, but using the
factory is generally preferred for
better control and flexibility.

13. 98) In UVM, what does the following code do?
uvm_factory::set_type_override_by_name("base_tr
ansaction","derived_transaction");
• A. It permanently overrides the
base_transaction with
derived_transaction for the entire
simulation.
• B. It temporarily overrides the
base_transaction with
derived_transaction for the current test
only.
• C. It creates an instance of the
derived_transaction class.
• D. It swaps the two classes during
execution.
• This line of code tells the UVM factory
to substitute every instance of
base_transaction with derived_transaction
whenever base_transaction is requested,
for the entire simulation. This override is
"permanent" in the sense that it applies
globally for the rest of the simulation,
unless explicitly changed.
Ans:
It permanently overrides the
base_transaction with
derived_transaction for the entire
simulation.

14. 99) What is the role of the uvm_config_db#()::set()
method in UVM?
• A. To create and connect UVM objects.
• B. To pass configuration settings to
UVM components and objects.
• C. To override the factory's default
behavior.
• D. To set the simulation time.
Ans:
To pass configuration settings to UVM
components and objects.
• A. To create and connect UVM
objects: This is the role of the
uvm_factory class.
• C. To override the factory's default
behavior: This can be done using
the uvm_config_db#()::set()
method, but it's not the primary
purpose.
• D. To set the simulation time: This
is done using the $time system
function.

15. 100) What is the correct method to stop a sequence
running on a sequencer in UVM?
A. stop_sequence()
B. kill()
C. disable_sequence()
D. finish_sequence()
Ans:
Stop_sequence()
• To stop a sequence running on a
sequencer in UVM, you can use
the sequencer.stop_sequences()
method. This method kills all
sequences and child sequences,
and removes all queued requests,
locks, and responses. This
effectively resets the sequencer
to an idle state