sequential logic circuits- Latch & Flip Flop.pdf

Combination Logic
 Logic that performs some transformation
operation on the inputs to produce outputs
which are simple logic functions of the input.
 The outputs reflect a function of the current
values on the inputs.
 There is not the capability to hold the value of
the input.

Sequential Logic
 Logic elements capable of storing a logic
value.
 Sequential circuits are those circuits that
employ these elements.
 Will be looking at the methodologies for
sequential circuit design.

Basic structure
 The basic structure of a synchronous sequential
circuit is shown here.
1) Synchronous – One input is a clock and on the clock
the next state becomes the present state of the
system.
2) Sequential – The circuit transitions between states
in a regular manner.

Definitions
 Inputs – All the outside logic signal inputs to the circuit.
◼ Typically, the clock is not consider part of the signal inputs of
the circuit.
 Outputs – The logic signal outputs.
 Present State – the logic value of all the state variables of
the system.
◼ These are stored in the state memory.
 Next State – Given the present state and the current values
on the inputs, the next state represents the next logic state
the circuit will transition to on the next clock.

Latch Circuit
 A latch is an electronic logic circuit that has two inputs and one
output.
◼ One of the inputs is called the SET input; the other is called the RESET
input.
 Latch circuits can be either active-high or active-low.
◼ The difference is determined by whether the operation of the latch circuit
is triggered by HIGH or LOW signals on the inputs.
a) Active-high circuit: Both inputs are normally tied to ground (LOW), and
the latch is triggered by a momentary HIGH signal on either of the inputs.
b) Active-low circuit: Both inputs are normally HIGH, and the latch is
triggered by a momentary LOW signal on either input.

Latch Circuit …
 In an active-high latch, both the SET and RESET inputs are
connected to ground.
◼ When the SET input goes HIGH, the output also goes HIGH.
◼ When the SET input returns to LOW, however, the output remains HIGH.
 The output of the active-high latch stays HIGH until the RESET input
goes HIGH.
◼ Then, the output returns to LOW and will go HIGH again only when the
SET input is triggered once more.
 In other words, the latch remembers that the SET input has been
activated.
◼ If the SET input goes HIGH for even a moment, the output goes HIGH and
stays HIGH, even after the SET input returns to LOW.
◼ The output returns to LOW only when the RESET input goes HIGH.

Latch Circuit …
 On the other hand, in an active-low latch the inputs are
normally held at HIGH.
◼ When the SET input momentarily goes LOW, the output goes HIGH.
◼ The output then stays HIGH until the RESET input momentarily goes
LOW.
 Note that most latch circuits actually have a second output that
is simply the first output inverted.
◼ In other words, whenever the first output is HIGH, the second output is
LOW, and vice versa.
◼ These outputs are usually referred to as Q and Q-bar with the latter
notated as follows:

Latch Circuit …
 The notation is usually pronounced either “bar Q” or “Q bar,”
though some people pronounce it “not Q.”
◼ The horizontal bar symbol over a label is a common logical shorthand for
inversion.
◼ That is, Q-bar is the inverse of Q. If Q is HIGH, Q-bar is LOW, and if Q is
LOW, Q-bar is HIGH.
 You can easily create an active-high latch from a pair of NOR gates.
◼ The output of a NOR gate is HIGH if both inputs are LOW; otherwise, the
output is LOW.
 In this circuit, the SET input is connected to one of the inputs of the
first NOR gate, and the RESET input is connected to one of the
inputs of the second NOR gate.

Latch Circuit …
 The trick of the latch circuit is that the output of the NOR
gates are cross-connected to the remaining NOR gate inputs.
◼ In other words, the output from the first NOR gate is connected to one
of the inputs of the second NOR gate, and the output from the second
NOR gate is connected to one of the inputs of the first NOR gate.

Latch Circuit …
 The next schematic is for an active-low latch.
◼ The only difference between this schematic and the one shown
previously is that the active-low latch uses NAND gates instead of NOR
gates.
◼ Notice also in this diagram that the inputs are referred to as SET-bar
and RESET-bar rather than SET and RESET, which indicates that the
inputs are active-low.

Different types of Latch
1) SR Latch
◼ Gated SR Latch
2) D latch

The SR Latch
 The SR (Set-Reset) Latch (With NAND Gates)
 And its operation

The waveform
 A simulation waveform would look
something like this

Other implementations of the SR
 With NAND Gates
 And adding a
control input

The D Latch
 The most common element in today’s VLSI

The D (or Data) Latch
 The most common element in today’s VLSI

Another implementation
 The implementation used in VLSI used
properties of the technology to reduce
circuit elements and power consumption.

The VLSI implemention
 The VLSI implementation uses the
transmission gate.
◼ With control input of 1 the input = the output
◼ With control input of 0 it is an open circuit
◼ Used inverter feedback pair to store state.
◼ Transmission gate requires 2 transistors.
◼ Inverts require 2 transistors
◼ T-gate Latch – 8 or 10 transistors (depends on
availability of clk’

Contrast with the gate circuit
 The D latch circuit in the text would take 18
transistors in a VLSI circuit.
 This is contrasted to 8 or 10 transistors.

Synchronous vs. Asynchronous
There are two types of sequential circuits:
 Synchronous sequential circuit: circuit output
changes only at some discrete instants of time.
This type of circuits achieves synchronization by
using a timing signal called the clock.
 Asynchronous sequential circuit: circuit output
can change at any time (clockless).

Clock Signal
Different duty cycles
Clock generator: Periodic train of clock pulses

Synchronous Sequential Circuits:
Flip flops as state memory
◼ The flip-flops receive their inputs from the
combinational circuit and also from a clock signal with
pulses that occur at fixed intervals of time, as shown in
the timing diagram.

SR Latch (NAND version)
S’
R’
Q
Q’
0 0
0 1
1 0
1 1
S’ R’ Q Q’
0
1
1
0
1 0 Set
0 0 1
0 1 1
1 0 1
1 1 0
X Y NAND

S’
R’
Q
Q’
0 0
0 1
1 0
1 1
S’ R’ Q Q’
1
1
1
0 1 0 Hold
0 0 1
0 1 1
1 0 1
1 1 0
X Y NAND
1 0 Set

S’
R’
Q
Q’
0 0
0 1
1 0
1 1
S’ R’ Q Q’
1
0
0
1
0 0 1
0 1 1
1 0 1
1 1 0
X Y NAND
1 0 Hold
1 0 Set
0 1 Reset

S’
R’
Q
Q’
0 0
0 1
1 0
1 1
S’ R’ Q Q’
1
1
0
1
0 0 1
0 1 1
1 0 1
1 1 0
X Y NAND
0 1 Hold
1 0 Set
0 1 Reset
1 0 Hold

S’
R’
Q
Q’
0 0
0 1
1 0
1 1
S’ R’ Q Q’
0
0
1
1
0 0 1
0 1 1
1 0 1
1 1 0
X Y NAND
0 1 Hold
1 0 Set
0 1 Reset
1 0 Hold
1 1 Disallowed

SR Latch with Clock signal
Latch is sensitive to input changes ONLY when C=1

D Latch
 One way to eliminate the undesirable
indeterminate state in the RS flip flop is to ensure
that inputs S and R are never 1 simultaneously.
 This is done in the D latch:

Difference between Latch and Flip-Flop
 Latches and flip-flops are the basic elements for storing
information.
◼ One latch or flip-flop can store one bit of information.
◼ The main difference between latches and flip-flops is that for latches,
their outputs are constantly affected by their inputs as long as the
enable signal is asserted.
◼ In other words, when they are enabled, their content changes
immediately when their inputs change.
 Flip-flops, on the other hand, have their content change only
either at the rising or falling edge of the enable signal.
◼ This enable signal is usually the controlling clock signal.
◼ After the rising or falling edge of the clock, the flip-flop content remains
constant even if the input changes.

Difference between Latch and Flip-Flop …

LATCH:
a) The fundamental latch is the simple SR flip-flop , where S and R stand for set
and reset respectively.
◼ It can be constructed from a pair of cross-coupled NOR logic gates.
b) Latches are level sensitive.
c) Latch is sensitive to duration of pulse and can send or receive the data when
the switch is on.
d) Latch is a device which continuously checks all its input and
correspondingly changes its output, independent of the time determined by
clocking signal.
e) It is based on enable function input
f) It is a level triggered , it mean that the output of present state and input of
the next state depends on the level that is binary input 1 or 0.

FLIP-FLOP:
a) Flip-Flop are edge sensitive.
b) Flip-Flop is sensitive to signal change and not on level.
◼ They can transfer data only at the single instant and data cannot be changed
until next signal change.
◼ Flip-flops are used as a register.
c) A flip-flop continuously checks its inputs and correspondingly
changes its output only at times determined by clocking signal.
d) It work's on the basis of clock pulses.
e) It is a edge triggered , it mean that the output and the next state
input changes when there is a change in clock pulse whether it
may a +ve or -ve clock pulse.

So commonly Flip- Flop and latches are.....
➢ Flip flops are edge-triggered devices whereas
latches are level triggered devices.
➢ latch does not have clock signal whereas flip
flop does.
➢ Flip flop has two values while latch has only
one value

Flip-flop Latch
A flip-flop samples the inputs only at a clock event
(rising edge, etc.)
A Latch samples the inputs continuously whenever
it is enabled, that is, only when the enable signal is
on. (or otherwise, it would be a wire, not a latch).
Flip-Flop are edge sensitive. Latches are level sensitive.
Flip-flop is sensitive to signal change and not on
level. They can transfer data only at the single
instant and data cannot be changed until next
signal change.
Latch is sensitive to duration of pulse and can
send or receive the data when the switch is on.
A flip-flop continuously checks its inputs and
correspondingly changes its output only at times
determined by clocking signal.
Latch is a device which continuously checks all its
input and correspondingly changes its output,
independent of the time determined by clocking
signal.
It work's on the basis of clock pulses. It is based on enable function input
It is a edge triggered , it mean that the output and
the next state input changes when there is a
change in clock pulse whether it may a +ve or -ve
clock pulse.
It is a level triggered , it mean that the output of
present state and input of the next state depends
on the level that is binary input 1 or 0.

Flip-Flops (or bistable gates)
 Flip-flops, also called bistable gates, are digital logic circuits that can be in
one of two states.
◼ Flip-flops maintain their state indefinitely until an input pulse called a trigger is
received.
◼ When a trigger is received, the flip-flop outputs change state according to
defined rules and remain in those states until another trigger is received.
 Flip-flop circuits are interconnected to form the logic gates for the digital
integrated circuits (IC s) used in memory chips and microprocessors.
◼ Flip-flops can be used to store one bit, or binary digit, of data.
◼ The data may represent the state of a sequencer, the value of a counter, an ASCII
character in a computer's memory or any other piece of information.

Flip-Flops (or bistable gates) …
 There are several different kinds of flip-flop circuits, with designators such
as
◼ T (toggle),
◼ S-R (set/reset)
◼ J-K (possibly named for Jack Kilby) and
◼ D (delay or data)
 A flip-flop typically includes zero, one, or two input signals as well as a
clock signal and an output signal.
◼ Some flip-flops also include a clear input signal to reset the current output.
 The first electronic flip-flop was invented in 1919 by W. H. Eccles and F. W.
Jordan.
◼ It used vacuum tubes and was initially called the Eccles-Jordan trigger circuit.

Flip-Flops
 Flip – flop is an electronic device which is having two stable states and a feedback
path which is used to store 1 – bit of information by using the clock signal as input.
 Latches are also used to do the same task except that they do not use a clock signal.
◼ Hence to say it simply, “Flip – flops are clocked latches”.
 They are used to store only 1 – bit of information and it can remain in the same state
until the clock signal affects the state of the input.
 There are four types of flip – flops
1) SR flip – flop
2) D flip – flop
3) JK flip – flop
4) T flip – flop

Flip-Flops …
 Generally, JK flip – flops and D flip – flops are the most widely used flip –
flops.
◼ And so their availability in the form of integrated circuits (IC’s) is abundant.
 Numerous varieties of JK flip – flop and D flip – flop are available in the
semiconductor market.
 The less popular SR flip – flop and T flip – flop are not available in the
market as integrated circuits (IC’s) (even though a very few number of SR
flip – flops are available as IC’s, they are not frequently used).
 There might be a situation where the less popular flip – flops are required in
order to implement a logic circuit.

Flip-Flops …
 In order use the less popular flip – flops, we will convert one type of flip –
flop into another.
 Some of the most common flip – flop conversions are
1) SR Flip – flop to JK Flip – flop
2) SR Flip – flop to D Flip – flop
3) SR Flip – flop to T Flip – flop
4) JK Flip – flop to SR Flip – flop
5) JK Flip – flop to D Flip – flop
6) JK Flip – flop to T Flip – flop
7) D Flip – flop to SR Flip – flop
8) D Flip – flop to JK Flip – flop

Flip-Flops …
 In order to convert one flip – flop to other type of flip – flop, we
should design a combinational circuit that is connected to the
actual flip – flop.
 Inputs to combinational circuit are same as the inputs of the
desired flip – flop.
 Outputs of combinational circuit are same as the inputs of the
available flip – flop.
 So the output of combinational circuit is connected to the input
of our available flip – flop.

Flip-Flops …
 The pictorial representation of the same is shown below.

Characteristic Table &
Excitation Table in a Flip-flop
 A characteristic table has the control input (i.e., D or T) as the
first column, the current state as the middle column, and the
next state as the last column.
◼ Basically, it tells you how the control bit affects the current state to
produce the next state.
 An excitation table has the current state as the first column, the
next state as the second column, and the control bit as the third
column.
◼ Basically, think of this as the state you have (first column), the state you
want (second column), and what you must set the control bit (third
column) to get the desired state you want.

Flip-Flops
 Latches are “transparent” (= any change on
the inputs is seen at the outputs
immediately).
 This causes synchronization problems.
 Solution: use latches to create flip-flops
that can respond (update) only on specific
times (instead of any time).
 Types: RS flip-flop and D flip-flop

S R CLK Q Q’
0 0 1 Q0 Q0’ Store
0 1 1 0 1 Reset
1 0 1 1 0 Set
1 1 1 1 1 Disallowed
X X 0 Q0 Q0’ Store
Master-Slave FF configuration
using SR latches (cont.)
•When C=1, master is enabled and
stores new data, slave stores old
data.
•When C=0, master’s state passes
to enabled slave, master not
sensitive to new data (disabled).

Edge-triggered Flip-Flops
 D-Type Positive Edge-Triggered Flip-Flop:

Characteristic Tables
 Defines the logical properties of a flip-flop
(such as a truth table does for a logic gate).
 Q(t) – present state at time t
 Q(t+1) – next state at time t+1

Characteristic Tables (cont.)
SR Flip-Flop
S R Q(t+1) Operation
0 0 Q(t) No change/Hold
0 1 0 Reset
1 0 1 Set
1 1 ? Undefined/Invalid

Characteristic Tables (cont.)
D Flip-Flop
D Q(t+1) Operation
0 0 Set
1 1 Reset
Characteristic Equation: Q(t+1) = D(t)

D Flip-Flop Timing Parameters
Setup time Hold time

The JK Flip Flop
 we now know that the basic gated SR NAND flip flop
suffers from two basic problems:
➢ the S = 0 and R = 0 condition (S = R = 0) must always be
avoided, and
➢ if S or R change state while the enable input is high the
correct latching action may not occur.
➢ Then to overcome these two fundamental design
problems with the SR flip-flop design, the JK flip Flop
was developed.

The JK Flip Flop …
 It is the most widely used of all the flip-flop designs and is
considered to be a universal flip-flop circuit.
 The sequential operation of the JK flip flop is exactly the same as
for the previous SR flip-flop with the same “Set” and “Reset”
inputs.
➢ The difference this time is that the “JK flip flop” has no invalid or
forbidden input states of the SR Latch even when S and R are
both at logic “1”.

 The JK flip flop is basically a gated SR Flip-flop Loading product
data.
 with the addition of a clock input circuitry that prevents the
illegal or invalid output condition that can occur when both
inputs S and R are equal to logic level “1”.
 Due to this additional clocked input, a JK flip-flop has four
possible input combinations, “logic 1”, “logic 0”, “no change”
and “toggle”.
◼ The symbol for a JK flip flop is similar to that of an SR Bistable Latch as
seen in the previous tutorial except for the addition of a clock input.

 Both the S and the R inputs of the previous SR bistable have
now been replaced by two inputs called the J and K inputs,
respectively after its inventor Jack Kilby.
◼ Then this equates to: J = S and K = R.
 The two 2-input AND gates of the gated SR bistable have now
been replaced by two 3-input NAND gates with the third input
of each gate connected to the outputs at Q and Q-bar.
◼ This cross coupling of the SR flip-flop allows the previously invalid
condition of S = “1” and R = “1” state to be used to produce a “toggle
action” as the two inputs are now interlocked.

 If the circuit is now “SET” the J input is inhibited by
the “0” status of Q-Bar through the lower NAND gate.
◼ If the circuit is “RESET” the K input is inhibited by the “0”
status of Q through the upper NAND gate.
◼ As Q and Q-Bar are always different we can use them to
control the input.
 When both inputs J and K are equal to logic “1”, the JK
flip flop toggles as shown in the truth table.

The Truth Table for the JK Function
same as
for the
SR Latch
Input Output
Description
J K Q Q-Bar
0 0 0 0 Memory
no change
0 0 0 1
0 1 1 0
Reset Q » 0
0 1 0 1
1 0 0 1
Set Q » 1
1 0 1 0
toggle
action
1 1 0 1
Toggle
1 1 1 0

The Master-Slave JK Flip-flop
 The Master-Slave Flip-Flop is basically two gated SR flip-flops
connected together in a series configuration with the slave
having an inverted clock pulse.
 The outputs from Q and Q from the “Slave” flip-flop are fed
back to the inputs of the “Master” with the outputs of the
“Master” flip flop being connected to the two inputs of the
“Slave” flip flop.
 This feedback configuration from the slave’s output to the
master’s input gives the characteristic toggle of the JK flip flop.

The Master-Slave JK Flip-flop : Truth
Table
 E(Enable)=clk

The T (or TOGGLE) Flip-flop
 Toggle flip flop is basically a JK flip flop with J and K terminals permanently
connected together.
 It has only input denoted by T as shown in the Symbol Diagram.
 The symbol for positive edge triggered T flip flop is shown below
Symbol Diagram Block Diagram

The T Flip-flop :Truth Table
 Operation:
S.N. Condition Operation
1
T = 0,
J = K = 0
The output Q and Q bar won't change
2
T = 1,
J = K = 1
Output will toggle corresponding to every
leading edge of clock signal.

Triggering of Flip Flops
 After going through my post on flip flop, you must have
understood the importance of triggering a flip flop.
 The output of a flip flop can be changed by bring a small
change in the input signal.
◼ This small change can be brought with the help of a clock pulse or
commonly known as a trigger pulse.
 When such a trigger pulse is applied to the input, the output
changes and thus the flip flop is said to be triggered.
 There are mainly four types of pulse-triggering methods.
◼ They differ in the manner in which the electronic circuits respond to
the pulse.

1. High Level Triggering
 When a flip flop is required to respond at its HIGH state, a
HIGH level triggering method is used.
 It is mainly identified from the straight lead from the clock
input.

2. Low Level Triggering
 When a flip flop is required to respond at its LOW state, a
LOW level triggering method is used.
 It is mainly identified from the clock input lead along with a low
state indicator bubble.

3. Positive Edge Triggering
 When a flip flop is required to respond at a LOW to HIGH
transition state, POSITIVE edge triggering method is used.
 It is mainly identified from the clock input lead along with a
triangle.

4. Negative Edge Triggering
 When a flip flop is required to respond during the HIGH to
LOW transition state, a NEGATIVE edge triggering method is
used.
 It is mainly identified from the clock input lead along with a
low-state indicator and a triangle.

Clock Pulse Transition
 The movement of a trigger pulse is always from a 0 to 1 and
then 1 to 0 of a signal.
 Thus it takes two transitions in a single signal.
◼ When it moves from 0 to 1 it is called a positive transition and when it
moves from 1 to 0 it is called a negative transition.

Edge-Triggered Flip-flops
 An edge-triggered flip-flop changes states either at the positive
edge (rising edge) or at the negative edge (falling edge) of the
clock pulse on the control input.
 The three basic types are introduced here: S-R, J-K and D.
 Notice the small triangle, called the dynamic input indicator, is
used to identify an edge-triggered flip-flop.
 There are of –
◼ Positive edge-triggered (without bubble at Clock input): S-R, J-K, and D.
◼ Negative edge-triggered (with bubble at Clock input): S-R, J-K, and D.

Edge-Triggered Flip-flops …
 The S-R, J-K and D inputs are called synchronous inputs because
data on these inputs are transferred to the flip-flop's output
only on the triggering edge of the clock pulse.
 On the other hand, the direct set (SET) and clear (CLR) inputs
are called asynchronous inputs, as they are inputs that affect the
state of the flip-flop independent of the clock.
 For the synchronous operations to work properly, these
asynchronous inputs must both be kept LOW.

1. Edge-triggered S-R flip-flop
 The operation and truth table for a negative edge-triggered
flip-flop are the same as those for a positive except that the
falling edge of the clock pulse is the triggering edge.
 As S = 1, R = 0. Flip-flop SETS on the rising clock edge.

1. Edge-triggered S-R flip-flop …
 Note that the S and R inputs can be changed at any time when
the clock input is LOW or HIGH (except for a very short
interval around the triggering transition of the clock) without
affecting the output.
 This is illustrated in the timing diagram below:

2. Edge-triggered J-K flip-flop
 The J-K flip-flop works very similar to S-R flip-flop.
◼ The only difference is that this flip-flop has NO invalid state.
 The outputs toggle (change to the opposite state), when both J
and K inputs are HIGH.
 The truth table is shown below.

3. Edge-triggered D flip-flop
 The operations of a D flip-flop is much more simpler.
◼ It has only one input addition to the clock.
◼ It is very useful when a single data bit (0 or 1) is to be stored.
◼ If there is a HIGH on the D input when a clock pulse is applied, the flip-
flop SETs and stores a 1.
◼ If there is a LOW on the D input when a clock pulse is applied, the flip-
flop RESETs and stores a 0.
 The truth table below summarize the operations of the
positive edge-triggered D flip-flop.
◼ As before, the negative edge-triggered flip-flop works the same except
that the falling edge of the clock pulse is the triggering edge.

sequential logic circuits- Latch & Flip Flop.pdf

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