The document contains VHDL code that implements a Moore finite state machine (FSM) with 3 states (s1, s2, s3) to detect a sequence of 3 ones. The FSM has an input x, a clock clk, a reset rst, and an output z. It transitions between states and sets z based on the current state and value of x on each clock edge. A testbench simulates the FSM by applying a repeating sequence of ones to x over multiple clock cycles while monitoring z.

1. Code: (Sequence Detector for 111)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FSM is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
x : in STD_LOGIC;
z : out STD_LOGIC);
end FSM;
architecture Behavioral of FSM is
type state_type is (s1,s2,s3);
signal state :state_type;
begin
-- Sequential memory of the VHDL MOORE FSM Sequence Detector
process(clk,rst)
begin
if(rst='1') then
state <= s1;
z<='0';
elsif(clk'event and clk='1') then
case state is
when s1=>
if x='1' then
state <= s2;
z<='0';
else
state <= s1;
z<='0';
end if;
when s2=>

2. if x='1' then
state <= s3;
z<='0';
else
state <= s1;
z<='0';
end if;
when s3=>
if x='1' then
state <= s1;
z<='1';
else
state <= s1;
z<='0';
end if;
end case;
end if;
end process;
end Behavioral;

3. Code: (Test bench )
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TB_FSM IS
END TB_FSM;
ARCHITECTURE behavior OF TB_FSM IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT FSM
PORT(
clk : IN std_logic;
rst : IN std_logic;
x : IN std_logic;
z : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal x : std_logic := '0';
--Outputs

4. signal z : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: FSM PORT MAP (
clk => clk,
rst => rst,
x => x,
z => z
);
-- Clock process definitions
process
begin
clk <= '0';
wait for 10ns;
clk <= '1';
wait for 10ns;
end process;
process
begin
rst <= '1';
wait for 10ns;
rst <= '0';
wait ;

5. end process;
process
begin
x <= '1';
wait for 10ns;
x <= '1';
wait for 10ns;
x <= '1';
wait for 10ns;
x <= '1';
wait for 10ns;
x <= '1';
wait for 10ns;
x <= '1';
wait for 10ns;
x <= '1';
wait for 10ns;
x <= '1';
wait for 10ns;
x <= '1';
wait for 10ns;
x <= '1';
wait for 10ns;
end process;
END;

6. Output: