VERILOG

1. Vijay Savani @ 2013 1
Verilog Codes
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2. Vijay Savani @ 2013 2
Combinational Circuits
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3. Vijay Savani @ 2013 3
Half Adder
• Gate Level Modelling
module half_adder (in_x, in_y, out_sum, out_carry);
input in_x;
input in_y;
output out_sum;
output out_carry;
xor x1(out_sum,in_x,in_y);
and a1(out_carry,in_x,in_y);
endmodule
• Dataflow Modelling
module half_adder (in_x, in_y, out_sum, out_carry);
assign out_sum = in_x ^ in_y;
assign out_carry = in_x & in_y;
endmodule
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4. 4
Half Adder
• Behavioral Modelling
module halfadder4(input x, y, output reg s, c);
always@(x or y)
begin
if (x == 0 && y == 0)
begin
s = 0; c = 0;
end
else if (x == 1 && y == 1)
begin
s = 0; c = 1;
end
else
begin
s = 1; c = 0;
end
end
endmodule
10/22/2019 Vijay Savani @ 2013

5. Vijay Savani @ 2013 5
• Gate Level Modelling
module fa(s,co,a,b,ci);
output s,co;
input a,b,ci;
xor1 u1(s,a,b,ci);
and1 u2(n1,a,b);
and1 u3(n2,b,ci);
and1 u4(n3,a,ci);
or1 u5(co,n1,n2,n3);
endmodule
• Dataflow Modelling
module fulladd ( input [3:0] a, input [3:0] b, input c_in, output c_out, output [3:0] sum);
assign {c_out, sum} = a + b + c_in;
endmodule
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Full Adder

6. Vijay Savani @ 2013 6
• Behavioral Modelling
module fulladd (input [3:0] a,
input [3:0] b,
input c_in,
output reg c_out,
output reg [3:0] sum);
always @ (a or b or c_in)
Begin
{c_out, sum} = a + b + c_in;
end
endmodule
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Full Adder

7. Vijay Savani @ 2013 7
• Structural Modelling
module full_use_half(
input a,
input b,
input cin,
output sum,
output carry
);
wire x,y,z;
halfadder HA1(a,b,y,x);
halfadder HA2(cin,y,sum,z);
or R1(carry,x,z);
endmodule
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Full Adder

8. 8
Half Subtractor
• Gate Level Modelling
module half_sub (in_x, in_y, out_diff, out_borrrow);
input in_x;
input in_y;
output out_diff;
output out_borrow;
Wire not_x;
xor x1(out_diff,in_x,in_y);
Not n1(not_x,in_x);
and a1(out_borrow,not_x,in_y);
endmodule
• Dataflow Modelling
module half_sub (in_x, in_y, out_diff, out_borrrow);
assign out_diff = in_x ^ in_y;
assign out_borrow = ~in_x & in_y;
endmodule
10/22/2019 Vijay Savani @ 2013

9. 9
Half Subtractor
• Gate Level Modelling
module half_sub (in_x, in_y, out_diff, out_borrrow);
input in_x;
input in_y;
output out_diff;
output out_borrow;
Wire not_x;
xor x1(out_diff,in_x,in_y);
Not n1(not_x,in_x);
and a1(out_borrow,not_x,in_y);
endmodule
• Dataflow Modelling
module half_sub (in_x, in_y, out_diff, out_borrrow);
assign out_diff = in_x ^ in_y;
assign out_borrow = ~in_x & in_y;
endmodule
10/22/2019 Vijay Savani @ 2013

10. 10
Full Subtractor
• Dataflow Modelling
module full_sub(
input a,
input b,
input c,
output diff,
output borrow
);
assign x= b^c;
assign diff = a ^ x;
assign n1=~c;
assign y=b & n1;
assign n2=~x;
assign z=a & n2;
assign borrow = y | z;
endmodule
10/22/2019 Vijay Savani @ 2013

11. Vijay Savani @ 2013 11
• Gate Level Modelling
module mux(
input [3:0] x,
input [1:0] s,
output mux_out
);
wire a,b,c,d,e,f;
not g1(a,s[1]);
not g2(b,s[0]);
and g3(c,x[0],a,b);
and g4(d,x[1],a,s[0]);
and g5(e,x[2],s[1],b);
and g6(f,x[3],s[1],s[0]);
or g7(out,c,d,e,f);
endmodule
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4x1 Mutiplexer

12. Vijay Savani @ 2013 12
• Dataflow Modelling
module mux_4to1_assign ( input [3:0] a,
input [3:0] b,
input [3:0] c,
input [3:0] d,
input [1:0] sel,
output [3:0] out);
assign out = sel[1] ? (sel[0] ? d : c) : (sel[0] ? b : a);
endmodule
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4x1 Mutiplexer

13. Vijay Savani @ 2013 13
4x1 Mutiplexer
• Behavioral Modelling
module mux_4to1_case ( input [3:0] a,
input [3:0] b,
input [3:0] c,
input [3:0] d,
input [1:0] sel,
output reg [3:0] out);
always @ (a or b or c or d or sel)
Begin
case (sel)
2'b00 : out <= a;
2'b01 : out <= b;
2'b10 : out <= c;
2'b11 : out <= d;
endcase
End
endmodule
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14. Vijay Savani @ 2013 14
4x1 Mutiplexer
• Structural Modelling
module mux2x1(out,a,b,s);
input a,b,s;
wire and_1,and_2,s_c;
output out;
not (s_c,s);
and (and_1,a,s_c);
and (and_2,b,s);
or (out,and_1,and_2);
endmodule
module mux4x1(out,i0,i1,i2,i3,s1,s0);
input i0,i1,i2,i3,s1,s0;
output out;
wire mux1,mux2;
mux2x1 mux_1(mux1,i0,i1,s1);
mux2x1 mux_2(mux2,i2,i3,s1);
mux2x1 mux_3(out,mux1,mux2,s0);
endmodule
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15. Vijay Savani @ 2013 15
3x8 Decoder
• Dataflow Modelling
module decoder_3to8(
input [2:0] a,
output [7:0] d );
assign d[0]=(~a[2])&(~a[1])&(~a[0]);
assign d[1]=(~a[2])&(~a[1])&(a[0]);
assign d[2]=(~a[2])&(a[1])&(~a[0]);
assign d[3]=(~a[2])&(a[1])&(a[0]);
assign d[4]=(a[2])&(~a[1])&(~a[0]);
assign d[5]=(a[2])&(~a[1])&(a[0]);
assign d[6]=(a[2])&(a[1])&(~a[0]);
assign d[7]=(a[2])&(a[1])&(a[0]);
endmodule
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16. Vijay Savani @ 2013 16
3x8 Decoder
• Structural Modelling
module decoder_struct(
input [2:0] a,
output [7:0] d
);
wire x,y,z;
not g1(z,a[0]);
not g2(y,a[1]);
not g3(x,a[2]);
and g4(d[0],x,y,z);
and g5(d[1],x,y,a[0]);
and g6(d[2],x,a[1],z);
and g7(d[3],x,a[1],a[0]);
and g8(d[4],a[2],y,z);
and g9(d[5],a[2],y,a[0]);
and g10(d[6],a[2],a[1],z);
and g11(d[7],a[2],a[1],a[0]);
endmodule
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17. Vijay Savani @ 2013 17
3x8 Decoder
• Behavioral Modelling
module decoder3to8(
Data_in,
Data_out
);
input [2:0] Data_in;
output [7:0] Data_out;
reg [7:0] Data_out;
always @(Data_in)
case (Data_in)
3'b000 : Data_out = 8'b00000001;
3'b001 : Data_out = 8'b00000010;
3'b010 : Data_out = 8'b00000100;
3'b011 : Data_out = 8'b00001000;
3'b100 : Data_out = 8'b00010000;
3'b101 : Data_out = 8'b00100000;
3'b110 : Data_out = 8'b01000000;
3'b111 : Data_out = 8'b10000000;
default : Data_out = 8'b00000000;
endcase
endmodule
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18. Vijay Savani @ 2013 18
Sequential Circuits
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19. Vijay Savani @ 2013 19
SR-Latch
• Gate Level Modelling
module SR_latch_gate (input R,
input S,
output Q,
output Qbar);
nor (Q, R, Qbar);
nor (Qbar, S, Q);
Endmodule
• Dataflow Modelling
module SR_latch_dataflow (input R, input S, output Q, output Qbar);
assign Q_i = Q;
assign Qbar_i = Qbar;
assign Q = ~ (R | Qbar);
assign Qbar = ~ (S | Q);
endmodule
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20. Vijay Savani @ 2013 20
D-Flip Flop
module flop(input clk,
input [3:0] d,
output reg [3:0] q);
always @ (posedge clk)
q <= d;
endmodule
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21. Vijay Savani @ 2013 21
D-Flip Flop
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module dff(d,clock,reset,q,qb);
input d,clock,reset;
output reg q,qb;
always@(posedge clock)
begin
case({reset,d})
2'b00 :q=1'b0;
2'b01 :q=1'b1;
default: q=1'b0;
endcase
qb<=~q;
end
endmodule

22. Vijay Savani @ 2013 22
D-Flip Flop with Synchronous Reset
module flop(input clk,
Input reset,
input [3:0] d,
output reg [3:0] q);
always @ (posedge clk)
begin
if(reset == ‘0’)
q<=0;
else
q <= d;
end
endmodule
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23. Vijay Savani @ 2013 23
D-Flip Flop with Asynchronous Reset
module flop(input clk,
Input reset,
input [3:0] d,
output reg [3:0] q);
always @ (posedge clk, negedge reset)
begin
if(reset == ‘0’)
q<=0;
else
q <= d;
end
endmodule
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24. Vijay Savani @ 2013 24
SR-Flip Flop
module srff(s,r,clk,rst, q,qb);
input s,r,clk,rst;
output q,qb;
reg q,qb;
reg [1:0]sr;
always@(posedge clk,posedge
rst)
begin
sr={s,r};
if(rst==0)
begin
case (sr)
2'd1:q=1'b0;
2'd2:q=1'b1;
2'd3:q=1'b1;
default: begin end
endcase
end
else
begin
q=1'b0;
end
qb=~q;
end
end module
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25. Vijay Savani @ 2013 25
SR-Flip Flop
module SRflipflop(S,R, Clock, Q);
input S,R, Clock;
output Q;
reg Q;
always @(posedge Clock)
Q = S || ~R && Q; // Q+ = S + R'Q
endmodule
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26. Vijay Savani @ 2013 26
JK-Flip Flop
module JKflipflop(J,K, Clock, Q);
input J,K, Clock;
output Q;
reg Q;
always @(posedge Clock)
Q = J && ~Q || ~K && Q; // Q+ = JQ' + K'Q
endmodule
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27. Vijay Savani @ 2013 27
JK-Flip Flop
module jkflop(j,k,clk,rst,q);
input j,k,clk,rst;
output q;
reg q;
always @(posedge clk)begin
if(j==1 & k==1 & rst==0)begin
q = ~q; //Toggles
end
else if(j==1 & k==0 & rst==0)begin
q = 1; //Set
end
else if(j==0 & k==1)begin
q = 0; //Cleared
end
end
always @(posedge rst)begin
q = 0; //The reset normally has negligible delay and hence ignored.
end
endmodule
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28. Vijay Savani @ 2013 28
T-Flip Flop
module Tflipflop(T, Clock, Q);
input T, Clock;
output Q;
reg Q;
always @(posedge Clock)
Q = T ^ Q; // Q = T XOR Q
endmodule
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29. Vijay Savani @ 2013 29
T-Flip Flop
module tff_sync_reset (
data , // Data Input
clk , // Clock Input
reset , // Reset input
q // Q output
);
input data, clk, reset ;
output q;
reg q;
always @ ( posedge clk)
if (~reset) begin
q <= 1'b0;
end else if (data) begin
q <= !q;
end
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30. Vijay Savani @ 2013 30
Shift Register
module slsr(sl, sr, din, clk, reset,Q);
input sl, sr, din, clk, reset;
output [7:0] Q;
reg [7:0] Q;
always @ (posedge clk) begin
if (~reset) begin
if (sl) begin
Q <= #2 {Q[6:0],din};
end
else if (sr) begin
Q <= #2 {din, Q[7:1]};
end
end
end
always @ (posedge reset) begin
Q<= 8'b00000000;
end
endmodule
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31. Vijay Savani @ 2013 31
Up Counter
module upmodn (Ck, Q);
parameter n = 6;
input Ck;
output [3:0] Q;
reg [3:0] Q;
always @(posedge Ck)
if (Q == n)
Q <= 0;
else
Q <= Q + 1;
endmodule
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32. Vijay Savani @ 2013 32
Down Counter
module upmodn (Ck, Q);
parameter n = 6;
input Ck;
output [3:0] Q;
reg [3:0] Q;
always @(posedge Ck)
if (Q == 0)
Q <= n;
else
Q <= Q - 1;
endmodule
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33. Vijay Savani @ 2013 33
FSM (Mealy)
module det110(sin,clk,reset,y);
input sin,clk,reset;
output y;
reg y;
reg [1:0] r_reg,n_reg;
parameter s0=2'b00,s1=2'b01,s2=2'b10;
always @(posedge clk or posedge reset)
if (reset)
r_reg <= s0;
else
r_reg <= n_reg;
always @(r_reg or sin)
if (r_reg==s0 && sin==0) n_reg=s0;
else if (r_reg==s0 && sin==1) n_reg=s1;
else if (r_reg==s1 && sin==0) n_reg=s0;
else if (r_reg==s1 && sin==1) n_reg=s2;
else if (r_reg==s2 && sin==0) n_reg=s0;
else if (r_reg==s2 && sin==1) n_reg=s2;
always @(r_reg or sin)
if (r_reg==s2 && sin==0) y=1;
else y=0;
endmodule
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34. Vijay Savani @ 2013 34
FSM (Moore)
module det_101 ( input clk,
input rstn,
input in,
output out );
parameter IDLE = 0,
S1 = 1,
S10 = 2,
S101 = 3;
reg [2:0] cur_state, next_state;
assign out = cur_state == S101 ? 1 : 0;
always @ (posedge clk) begin
if (!rstn)
cur_state <= IDLE;
else
cur_state <= next_state;
end
always @ (cur_state or in) begin
case (cur_state)
IDLE : begin
if (in) next_state = S1;
else next_state = IDLE;
end
S1: begin
if (in) next_state = IDLE;
else next_state = S10;
end
S10 : begin
if (in) next_state = S101;
else next_state = IDLE;
end
S101 :
next_state = S1;
endcase
end
endmodule
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