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Problem Description and Analysis
In this Laboratory, you will design and simulate a simple ALU in Quatrus II Verilog. The
description and specification of the ALU is given below:
An ALU is a logic circuit that performs various Boolean and arithmetic operations on n-bit
operands. This ALU has 2 four-bit data inputs, A and B, a three-bit select input, S, and a four-bit
output, F. The functionality of this simple ALU is specified in the table below.
Operation
Inputs
S
Outputs
F
s2
s1
s0
f3
f2
f1
f0
Clear
0
0
0
0
0
0
0
B - A
0
0
1
B – A
A – B
0
1
0
A – B
ADD
0
1
1
A + B
XOR
1
0
0
A XOR B
OR
1
1
0
A OR B
AND
1
1
0
A AND B
Preset
1
1
1
1
1
1
1
Table 1 – Functionality Table for ALU
Operation
Inputs
S
Outputs
F
s2
s1
s0
f3
f2
f1
f0
Clear
0
0
0
0
0
0
0
B - A
0
0
1
B – A
A – B
0
1
0
A – B
ADD
0
1
1
A + B
XOR
1
0
0
A XOR B
OR
1
1
0
A OR B
AND
1
1
0
A AND B
Preset
1
1
1
1
1
1
1
Solution
module alu(s, A, B, F);
input [2:0] S;
input [3:0] A, B;
output reg [3:0] F;
always @(S, A, B)
case (S)
0: F = 0000;
1: F = B - A;
2: F = A - B;
3: F = A + B;
4: F = A ^ B;
5: F = A | B;
6: F = A & B;
7: F = 1111;
endcase
endmodule

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Problem Description and AnalysisIn this Laboratory, you will desig.pdf

  • 1. Problem Description and Analysis In this Laboratory, you will design and simulate a simple ALU in Quatrus II Verilog. The description and specification of the ALU is given below: An ALU is a logic circuit that performs various Boolean and arithmetic operations on n-bit operands. This ALU has 2 four-bit data inputs, A and B, a three-bit select input, S, and a four-bit output, F. The functionality of this simple ALU is specified in the table below. Operation Inputs S Outputs F s2 s1 s0 f3 f2 f1 f0 Clear 0 0 0 0 0 0 0 B - A 0 0 1 B – A A – B 0 1
  • 2. 0 A – B ADD 0 1 1 A + B XOR 1 0 0 A XOR B OR 1 1 0 A OR B AND 1 1 0 A AND B Preset 1 1 1 1 1 1 1 Table 1 – Functionality Table for ALU Operation Inputs S Outputs F
  • 3. s2 s1 s0 f3 f2 f1 f0 Clear 0 0 0 0 0 0 0 B - A 0 0 1 B – A A – B 0 1 0 A – B ADD 0 1 1 A + B XOR 1 0 0 A XOR B OR
  • 4. 1 1 0 A OR B AND 1 1 0 A AND B Preset 1 1 1 1 1 1 1 Solution module alu(s, A, B, F); input [2:0] S; input [3:0] A, B; output reg [3:0] F; always @(S, A, B) case (S) 0: F = 0000; 1: F = B - A; 2: F = A - B; 3: F = A + B; 4: F = A ^ B; 5: F = A | B; 6: F = A & B; 7: F = 1111; endcase endmodule