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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2012
Prescalers, Sintetizadores de Frequencia,
Lógica Diferencial CML
Prof. Jader A. De Lima
Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2012
Synchronous vs. asynchronous counters
Synchronous counters
• consume large power
• represent large CLOAD to oscillator
• race problems
Ex: if Q2 is slower to go to 0 than Q1 to go to 1, the
output of the AND gate experiences glitches.
Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2012
• delay almost constant between the input clock and the output at the divided
frequency (NOT proportional to no. of flip-flops)
Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2012
Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2012
Asynchronous counters
• forward/backward counting
• power consumption is reduced, as each stage operates at half frequency of previous stage
Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2012
• delay is however added between the input clock and the output at the divided
frequency (proportional to no. of flip-flops)
Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2012
Programmable dividers
(modulus-8 with backwards counting from Q3Q2Q1 =111 to 000)
Basic principle: to preset counter to a initial state P and detect final state F by means
of an ‘end-of-count’ EOC logic ⇒ the counter counts down between P and F
• limitation is max fin as correct operation is guaranteed if EOC signal presets the
counter before the next clock edge arrives
Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2012
PRESCALERS
resolution: F1
Frequency Synthesizers
Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2012
i) High-frequency operation is attained when logic function is kept simple
i) simplest dividers divide by fixed numbers
⇒ programmable divider could have a fixed-modulus high-speed divider as
first stage
• If a pre-settable modulus-P divider follows a modulus-N prescaler, overall
frequency division ratio is NxP.
• the input frequency has to be lowered exactly by P to keep same resolution
⇒ implies narrowing the PLL loop bandwidth, which may be undesirable!
Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2012
resolution degraded: P x F1
Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2012
Pulse Swallowing Technique
• If S input pulses are swallowed the output period becomes longer
by S reference periods
⇒ overall frequency division-ratio is M = (NP + S), which can be
varied in unity steps by changing S
M1= (NP + S)
M2= (NP + S+1)
⇒ ∆M = M2 – M1 = 1 (same resolution without prescaling!)
Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2012
• at beginning of counting, N+1 factor is selected
in dual-modulus prescaler (OUT = 1)
• P and S count in parallel, with P > S
• when S overflows, set = 1 and OUT → 0
• N factor is selected in dual-modulus prescaler
• it remains like that until P overflows and OUT
→ 1
• cycle is restarted.
high-speed
A= (N+1) A= N
total counts of Fout is a full F1 cycle:
S x (N+1) + (P-S)N
SN + S + PN – SN
PN + S = M
asynchronous counter
Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2012
total counts of Fout is a full F1 cycle:
S x (N+1) + (P-S)N
SN + S + PN – SN
PN + S = M
P > S
Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2012
Ex 1 (using pulse swallowing):
• frequency synthesizer in 2400–2480 MHz ISM band
• 1 MHz channel spacing ⇒ division factor (M = NP + S )
between 2400–2480
Design steps:
i)choice of the modulus N (dual-modulus prescaler), P (program
counter) and S (swallow counter), with P > S
ii)assume that only S can vary to simplify channel-select logic.
iii)make either N or N + 1 a power of two
iv)choose S as low as possible so that P > S is a minimum
Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2012
Assuming initially S varies between 1 and 81 (to cover 81 possible division ratios)
then P > 81:
6.29
81
2399
P
SM
N ==
−
<
Choosing N = 16 ⇒ 149
16
2399
N
SM
P ==
−
= and P > S
Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2012
MMIN = (Pmin × N) + Smin
= ((N +1) × N) + 1
= N2
+ N + 1
MMAX = (Pmax × N) + Smax
Pmax and Smax are determined by the size of P and S counters.
MMIN-MMAX: range over which it is possible to change N in
discrete integer steps.
M = (P × N) + S
Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2012
Ex2: assume that prescaler is programmed to N/N+1 = 32/33
S counter: 6 bits means S can be 26
– 1 = 63
P counter: 13 bits means P can be 213
– 1 = 8191
MMIN = N2
+ N +1 = 1057
MMAX = (Pmax × N) + Smax
= (8191 × 32) + 63 = 262175
If F1 = 10KHz and P = 6000; S =40
FOUT_MIN = 1.057GHz
FOUT_MAX = 2.62GHz
FOUT = F1 (PN + S) = 10KHz (6000x32+40)=1.92040GHz
FOUT1 = F1 (PN + S+1)= 10KHz (6000x32+41)=1.92041GHz
∆FOUT = 10KHz
Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2012
• The main building block of the before-described counters is the D-
type level-triggered latch
(Differential) CMOS Current Mode Logic - (D)CML
• CK swing has to be wide enough (VTH + VGO) to turn on pMOS. Since CK has a finite
slope, this implies a certain delay before the latch is able to sense at CK transition
⇒ Differential CML for high-speed processing
Conventional CMOS
Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2012
• CML is based on the use of differential stages
• tail current is switched between two branches by CK
• a regenerative pair holds the data when CK is low
• loads can be triode-operating or diode-connected PMOS.
Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2012
Single-Ended vs Differential
Common-Mode disturbances disappear in the differential output
Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2012
• small ∆Vin already develops full VOUT
Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2012
CML x CMOS
Pros:
i)reduced voltage swing (VGO against VGO + VTH of CMOS stages) ⇒
less delay before input sensing ⇒ higher speed
ii)current-steering operation: current drained from supply less variable
iii)differential circuits are immune to coupled disturbances; they reject
disturbances coming from substrate and power supply due to other blocks
Cons:
i)larger area
ii)2 “wires” per signal
iii)higher consumption
Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2012
- Emitter-Coupled Logic (origin)
Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2012
- Emitter-Coupled Logic
Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2012
CML AND / NAND gates
Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2012
CML OR / NOR gates
Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2012
Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2012

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Design of Mixed-Mode ICs - Module 2

  • 1. Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2012 Prescalers, Sintetizadores de Frequencia, Lógica Diferencial CML Prof. Jader A. De Lima
  • 2. Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2012 Synchronous vs. asynchronous counters Synchronous counters • consume large power • represent large CLOAD to oscillator • race problems Ex: if Q2 is slower to go to 0 than Q1 to go to 1, the output of the AND gate experiences glitches.
  • 3. Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2012 • delay almost constant between the input clock and the output at the divided frequency (NOT proportional to no. of flip-flops)
  • 4. Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2012
  • 5. Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2012 Asynchronous counters • forward/backward counting • power consumption is reduced, as each stage operates at half frequency of previous stage
  • 6. Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2012 • delay is however added between the input clock and the output at the divided frequency (proportional to no. of flip-flops)
  • 7. Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2012 Programmable dividers (modulus-8 with backwards counting from Q3Q2Q1 =111 to 000) Basic principle: to preset counter to a initial state P and detect final state F by means of an ‘end-of-count’ EOC logic ⇒ the counter counts down between P and F • limitation is max fin as correct operation is guaranteed if EOC signal presets the counter before the next clock edge arrives
  • 8. Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2012 PRESCALERS resolution: F1 Frequency Synthesizers
  • 9. Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2012 i) High-frequency operation is attained when logic function is kept simple i) simplest dividers divide by fixed numbers ⇒ programmable divider could have a fixed-modulus high-speed divider as first stage • If a pre-settable modulus-P divider follows a modulus-N prescaler, overall frequency division ratio is NxP. • the input frequency has to be lowered exactly by P to keep same resolution ⇒ implies narrowing the PLL loop bandwidth, which may be undesirable!
  • 10. Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2012 resolution degraded: P x F1
  • 11. Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2012 Pulse Swallowing Technique • If S input pulses are swallowed the output period becomes longer by S reference periods ⇒ overall frequency division-ratio is M = (NP + S), which can be varied in unity steps by changing S M1= (NP + S) M2= (NP + S+1) ⇒ ∆M = M2 – M1 = 1 (same resolution without prescaling!)
  • 12. Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2012 • at beginning of counting, N+1 factor is selected in dual-modulus prescaler (OUT = 1) • P and S count in parallel, with P > S • when S overflows, set = 1 and OUT → 0 • N factor is selected in dual-modulus prescaler • it remains like that until P overflows and OUT → 1 • cycle is restarted. high-speed A= (N+1) A= N total counts of Fout is a full F1 cycle: S x (N+1) + (P-S)N SN + S + PN – SN PN + S = M asynchronous counter
  • 13. Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2012 total counts of Fout is a full F1 cycle: S x (N+1) + (P-S)N SN + S + PN – SN PN + S = M P > S
  • 14. Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2012 Ex 1 (using pulse swallowing): • frequency synthesizer in 2400–2480 MHz ISM band • 1 MHz channel spacing ⇒ division factor (M = NP + S ) between 2400–2480 Design steps: i)choice of the modulus N (dual-modulus prescaler), P (program counter) and S (swallow counter), with P > S ii)assume that only S can vary to simplify channel-select logic. iii)make either N or N + 1 a power of two iv)choose S as low as possible so that P > S is a minimum
  • 15. Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2012 Assuming initially S varies between 1 and 81 (to cover 81 possible division ratios) then P > 81: 6.29 81 2399 P SM N == − < Choosing N = 16 ⇒ 149 16 2399 N SM P == − = and P > S
  • 16. Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2012 MMIN = (Pmin × N) + Smin = ((N +1) × N) + 1 = N2 + N + 1 MMAX = (Pmax × N) + Smax Pmax and Smax are determined by the size of P and S counters. MMIN-MMAX: range over which it is possible to change N in discrete integer steps. M = (P × N) + S
  • 17. Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2012 Ex2: assume that prescaler is programmed to N/N+1 = 32/33 S counter: 6 bits means S can be 26 – 1 = 63 P counter: 13 bits means P can be 213 – 1 = 8191 MMIN = N2 + N +1 = 1057 MMAX = (Pmax × N) + Smax = (8191 × 32) + 63 = 262175 If F1 = 10KHz and P = 6000; S =40 FOUT_MIN = 1.057GHz FOUT_MAX = 2.62GHz FOUT = F1 (PN + S) = 10KHz (6000x32+40)=1.92040GHz FOUT1 = F1 (PN + S+1)= 10KHz (6000x32+41)=1.92041GHz ∆FOUT = 10KHz
  • 18. Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2012 • The main building block of the before-described counters is the D- type level-triggered latch (Differential) CMOS Current Mode Logic - (D)CML • CK swing has to be wide enough (VTH + VGO) to turn on pMOS. Since CK has a finite slope, this implies a certain delay before the latch is able to sense at CK transition ⇒ Differential CML for high-speed processing Conventional CMOS
  • 19. Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2012 • CML is based on the use of differential stages • tail current is switched between two branches by CK • a regenerative pair holds the data when CK is low • loads can be triode-operating or diode-connected PMOS.
  • 20. Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2012 Single-Ended vs Differential Common-Mode disturbances disappear in the differential output
  • 21. Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2012 • small ∆Vin already develops full VOUT
  • 22. Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2012 CML x CMOS Pros: i)reduced voltage swing (VGO against VGO + VTH of CMOS stages) ⇒ less delay before input sensing ⇒ higher speed ii)current-steering operation: current drained from supply less variable iii)differential circuits are immune to coupled disturbances; they reject disturbances coming from substrate and power supply due to other blocks Cons: i)larger area ii)2 “wires” per signal iii)higher consumption
  • 23. Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2012 - Emitter-Coupled Logic (origin)
  • 24. Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2012 - Emitter-Coupled Logic
  • 25. Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2012 CML AND / NAND gates
  • 26. Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2012 CML OR / NOR gates
  • 27. Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2012
  • 28. Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2012