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Machine Trace Metrics

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Wang Hsiangkai
Wang Hsiangkai

1. The document describes methods for computing trace metrics like instruction depth, height, and critical path length for basic blocks. It involves analyzing data dependencies between instructions within and across blocks to determine earliest issue cycles while traversing the trace in postorder and inverse postorder. 2. Key steps include finding the best predecessor and successor blocks for each block, computing depth and height values bottom-up and top-down based on dependency latencies, and tracking register liveness across blocks to determine the overall critical path.

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Machine Trace Metrics
FixedBlockInfo • Per-basic block information that doesn’t depend on the trace through the block • The number of non-trivial instructions in the block. • Has calls or not. basic block the number of instructions
ProcResourceCycles (PRKinds = 5) PRCycles block 0 block 1 ProcResourceIdx The number of cycles consumed by block B on processor resource R is at ProcResourceCycles[B x Kinds + R] Processor Resources Cycles
TraceBlockInfo • Per-basic block information that relates to a specific trace through the block. • Trace predecessor • Trace successor • instruction depth • Accumulated number of instructions in the trace above this block. Does not include instructions in this block. • instruction height • Accumulated number of instructions in the trace below this block. Includes instructions in this block. basic block trace predecessor trace successor instruction depth instruction height
Compute Depth Resource - Update TraceBlockInfo BB PBB BB InstrDepth = 0 Head = BB number PBB InstrCount PBB InstrDepth InstrDepth = PBB InstrDepth + PBB InstrCount Head = PBB Head Trace Head Head Trace Tail Trace Tail Case 1: BB has no predecessor Case 2: BB has predecessor PBB
ProcResourceCycles (PRKinds = 5) PRcycle_r1 PRcycle_r2 PRcycle_r3 PRcycle_r4 PRcycle_r5 PBB BB ProcResourceDepths (PRKinds = 5) PRdepth_r1 PRdepth_r2 PRdepth_r3 PRdepth_r4 PRdepth_r5 PRdepth_r1 + PRcycle_r1 PRdepth_r2 + PRcycle_r2 PRdepth_r3 + PRcycle_r3 PRdepth_r4 + PRcycle_r4 PRdepth_r5 + PRcycle_r5 Compute Depth Resource - Update Processor Resource Depths
Trace Head Trace Tail Trace Head BB InstrHeight = BB InstrCount Tail = BB number BB SBB InstrHeight = BB instrCount + SBB InstrHeight Tail = SBB Tail SBB InstrHeight BB InstrCount Tail Case 1: BB has no successor Case 2: BB has successor SBB Compute Height Resource - Update TraceBlockInfo
ProcResourceCycles (PRKinds = 5) PRcycle_r1 PRcycle_r2 PRcycle_r3 PRcycle_r4 PRcycle_r5 SBB BB ProcResourceHeights (PRKinds = 5) PRheight_r1 PRheight_r2 PRheight_r3 PRheight_r4 PRheight_r5 PRheight_r1 + PRcycle_r1 PRheight_r2 + PRcycle_r2 PRheight_r3 + PRcycle_r3 PRheight_r4 + PRcycle_r4 PRheight_r5 + PRcycle_r5 Compute Height Resource - Update Processor Resource Heights
Pick Trace Predecessor BB PBB1 PBB2 PBB3 Trace Head PBB3 InstrDepth PBB2 InstrDepth PBB1 InstrDepth Best Depth = min (PBBn InstrDepth + PBBn InstCount) PBB1 InstrCount PBB2 InstrCount PBB3 InstrCount
Pick Trace Successor Trace Tail SBB1 SBB2 SBB3 BB SBB3 InstrHeight SBB2 InstrHeight SBB1 InstrHeight Best Height = min (SBBn InstrHeight)
• Inverse post-order traversal of predecessors. • Call pickTracePred() to find the best predecessor. • Compute depth resources • TraceBlockInfo • instruction depth, trace head, etc. • ProcResourceDepths[] • cycles count for each processor resources from trace head to the basic block, does not include cycles in the basic block. • Post-order traversal of successors. • Call pickTraceSucc() to find the best successor. • Compute height resources • TraceBlockInfo • instruction height, trace tail, etc. • ProcResourceHeights[] • cycles count for each processor resources from the basic block to trace tail, including cycles in the basic block. Compute Trace for Basic Block
Data Dependency • There are three elements in data dependency structure • Defining MachineInstr • Operand number in defining MachineInstr • Operand number in using MachineInstr • These three elements are used by Target Schedule Model to compute latency between defining and using instructions for operands.
Add LiveIn DefMBB: … Reg = … … Trace Tail BB #2 BB #1 Trace Head Add Reg to LiveIns for all successors LiveIns.push_back(Reg) LiveIns.push_back(Reg) LiveIns.push_back(Reg) Reg is a virtual register defined in DefMBB.
MIHeightMap & RegUnits … MI: DefOp, UseOp1, UseOp2 … I: DefOp2, DefOp, … … DefOp.Cycle (Height of I) Latency of DefOp (MI, I) Height = Latency + DefOp.Cycle // UseOp2 is a physical register. RegUnits[UseOp2].Cycle = max (RegUnits[UseOp2].Cycle, Height) RegUnits[UseOp2].MI = MI RegUnits[UseOp2[.Op = 2 Trace Tail … DI: UseOp1, … … Data dependency (DI, 0, 1) UseOp1 is virtual register DefOp is physical register Latency of UseOp1 (DI, MI) MIHeightMap.insert (DI, Latency of UseOp1 + Latency of DefOp + DefOp.Cycle)
MIHeightMap & RegUnits … MI: DefOp, UseOp1, UseOp2 … I: DefOp2, DefOp, … … DefOp.Cycle (Height of I) Latency of DefOp (MI, I) Height = Latency + DefOp.Cycle // UseOp2 is a physical register. RegUnits[UseOp2].Cycle = max (RegUnits[UseOp2].Cycle, Height) RegUnits[UseOp2].MI = MI RegUnits[UseOp2[.Op = 2 Trace Tail … DI: UseOp1, … … Data dependency (DI, 0, 1) DefOp is physical register Latency of UseOp1 (DI, MI) MIHeightMap.insert (DI, Latency of UseOp1 + Latency of DefOp + DefOp.Cycle) Computed by updatePhysDepsUpwards() UseOp1 is virtual register
MIHeightMap & RegUnits … MI: DefOp, UseOp1, UseOp2 … I: DefOp2, DefOp, … … DefOp.Cycle (Height of I) Latency of DefOp (MI, I) Height = Latency + DefOp.Cycle // UseOp2 is a physical register. RegUnits[UseOp2].Cycle = max (RegUnits[UseOp2].Cycle, Height) RegUnits[UseOp2].MI = MI RegUnits[UseOp2[.Op = 2 Trace Tail … DI: UseOp1, … … Data dependency (DI, 0, 1) DefOp is physical register Latency of UseOp1 (DI, MI) MIHeightMap.insert (DI, Latency of UseOp1 + Latency of DefOp + DefOp.Cycle) Computed by getDataDep() UseOp1 is virtual register
MIHeightMap & RegUnits … MI: DefOp, UseOp1, UseOp2 … I: DefOp2, DefOp, … … DefOp.Cycle (Height of I) Latency of DefOp (MI, I) Height = Latency + DefOp.Cycle // UseOp2 is a physical register. RegUnits[UseOp2].Cycle = max (RegUnits[UseOp2].Cycle, Height) RegUnits[UseOp2].MI = MI RegUnits[UseOp2[.Op = 2 Trace Tail … DI: UseOp1, … … Data dependency (DI, 0, 1) DefOp is physical register Latency of UseOp1 (DI, MI) MIHeightMap.insert (DI, Latency of UseOp1 + Latency of DefOp + DefOp.Cycle) Computed by pushDepHeight() UseOp1 is virtual register MIHeightMap[MI] or computed by updatePhysDepsUp wards() if MI contains physical registers
Compute Instruction Depth BB Trace Head BB #2 BB #1: … UseMI… for all instruction UseMI in BB #1: for all data dependency: Cycle = max (Cycles[DefMI].Depth + Latency (DefMI, UseMI)) Has valid instruction Depth. compute instruction depth from BB #1. Critical path length for basic block is maximum of Cycles[MI].Depth + Cycles[MI].Height for all instructions MI in basic block. … DefMI… data dependency Latency of (DefMI, UseMI) Cycles[DefMI].Depth Cycles[UseMI].Depth = Cycle
Compute Instruction Depth BB Trace Head BB #2 BB #1: … UseMI… for all instruction UseMI in BB #1: for all data dependency: Cycle = max (Cycles[DefMI].Depth + Latency (DefMI, UseMI)) Has valid instruction Depth. compute instruction depth from BB #1. Critical path length for basic block is maximum of Cycles[MI].Depth + Cycles[MI].Height for all instructions MI in basic block. … DefMI… data dependency Latency of (DefMI, UseMI) Cycles[DefMI].Depth Cycles[UseMI].Depth = Cycle 1. Get data dependency
Compute Instruction Depth BB Trace Head BB #2 BB #1: … UseMI… for all instruction UseMI in BB #1: for all data dependency: Cycle = max (Cycles[DefMI].Depth + Latency (DefMI, UseMI)) Has valid instruction Depth. compute instruction depth from BB #1. Critical path length for basic block is maximum of Cycles[MI].Depth + Cycles[MI].Height for all instructions MI in basic block. … DefMI… data dependency Latency of (DefMI, UseMI) Cycles[DefMI].Depth Cycles[UseMI].Depth = Cycle 2. Calculate UseMI’s cycle
Compute Instruction Depth BB Trace Head BB #2 BB #1: … UseMI… for all instruction UseMI in BB #1: for all data dependency: Cycle = max (Cycles[DefMI].Depth + Latency (DefMI, UseMI)) Has valid instruction Depth. compute instruction depth from BB #1. Critical path length for basic block is maximum of Cycles[MI].Depth + Cycles[MI].Height for all instructions MI in basic block. … DefMI… data dependency Latency of (DefMI, UseMI) Cycles[DefMI].Depth Cycles[UseMI].Depth = Cycle 3. Update UseMI’s Depth
Compute Instruction Height Trace Tail BB BB #2 BB #1: MI… Has valid instruction Height. Succ compute through the trace blocks in bottom-up order if MI has no physical registers: Cycle = Heights[MI] else Cycle = updatePhysDepsUpwards() update Heights according to data dependency Cycles[MI].Height = Cycle if LiveInReg is virtual register: LiveInReg.Height = Heights[DefMI] if LiveInReg is physical register LiveInReg.Height = RegUnit.Cycle
Compute Instruction Height Trace Tail BB BB #2 BB #1: MI… Has valid instruction Height. Succ compute through the trace blocks in bottom-up order if MI has no physical registers: Cycle = Heights[MI] else Cycle = updatePhysDepsUpwards() update Heights according to data dependency Cycles[MI].Height = Cycle if LiveInReg is virtual register: LiveInReg.Height = Heights[DefMI] if LiveInReg is physical register LiveInReg.Height = RegUnit.Cycle 1. Get data dependency
Compute Instruction Height Trace Tail BB BB #2 BB #1: MI… Has valid instruction Height. Succ compute through the trace blocks in bottom-up order if MI has no physical registers: Cycle = Heights[MI] else Cycle = updatePhysDepsUpwards() update Heights according to data dependency Cycles[MI].Height = Cycle if LiveInReg is virtual register: LiveInReg.Height = Heights[DefMI] if LiveInReg is physical register LiveInReg.Height = RegUnit.Cycle 2. Compute cycles of MI
Compute Instruction Height Trace Tail BB BB #2 BB #1: MI… Has valid instruction Height. Succ compute through the trace blocks in bottom-up order if MI has no physical registers: Cycle = Heights[MI] else Cycle = updatePhysDepsUpwards() update Heights according to data dependency Cycles[MI].Height = Cycle if LiveInReg is virtual register: LiveInReg.Height = Heights[DefMI] if LiveInReg is physical register LiveInReg.Height = RegUnit.Cycle 3. Update Heights[]
Compute Instruction Height Trace Tail BB BB #2 BB #1: MI… Has valid instruction Height. Succ compute through the trace blocks in bottom-up order if MI has no physical registers: Cycle = Heights[MI] else Cycle = updatePhysDepsUpwards() update Heights according to data dependency Cycles[MI].Height = Cycle if LiveInReg is virtual register: LiveInReg.Height = Heights[DefMI] if LiveInReg is physical register LiveInReg.Height = RegUnit.Cycle 4. Update MI’s Height
Compute Instruction Height Trace Tail BB BB #2 BB #1: MI… Has valid instruction Height. Succ compute through the trace blocks in bottom-up order if MI has no physical registers: Cycle = Heights[MI] else Cycle = updatePhysDepsUpwards() update Heights according to data dependency Cycles[MI].Height = Cycle if LiveInReg is virtual register: LiveInReg.Height = Heights[DefMI] if LiveInReg is physical register LiveInReg.Height = RegUnit.Cycle 5. Update LiveInReg’s Height
Compute Cross Block Critical Path BB LIR in BB’s LiveIns … LIR.Reg = … (DefMI) … Len = LIR.Height + Cycles[DefMI].Depth for all LIR in LiveIns, the maximum of Len is critical path length for the basic block BB. LIR.Height: Height of defining instruction Trace Head Cycles[DefMI].Depth: Earliest issue cycle as determined by data dependencies and instruction latencies from the beginning of the trace. Trace Tail LIR.Reg is a virtual register

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Machine Trace Metrics

  • 2. FixedBlockInfo • Per-basic block information that doesn’t depend on the trace through the block • The number of non-trivial instructions in the block. • Has calls or not. basic block the number of instructions
  • 3. ProcResourceCycles (PRKinds = 5) PRCycles block 0 block 1 ProcResourceIdx The number of cycles consumed by block B on processor resource R is at ProcResourceCycles[B x Kinds + R] Processor Resources Cycles
  • 4. TraceBlockInfo • Per-basic block information that relates to a specific trace through the block. • Trace predecessor • Trace successor • instruction depth • Accumulated number of instructions in the trace above this block. Does not include instructions in this block. • instruction height • Accumulated number of instructions in the trace below this block. Includes instructions in this block. basic block trace predecessor trace successor instruction depth instruction height
  • 5. Compute Depth Resource - Update TraceBlockInfo BB PBB BB InstrDepth = 0 Head = BB number PBB InstrCount PBB InstrDepth InstrDepth = PBB InstrDepth + PBB InstrCount Head = PBB Head Trace Head Head Trace Tail Trace Tail Case 1: BB has no predecessor Case 2: BB has predecessor PBB
  • 6. ProcResourceCycles (PRKinds = 5) PRcycle_r1 PRcycle_r2 PRcycle_r3 PRcycle_r4 PRcycle_r5 PBB BB ProcResourceDepths (PRKinds = 5) PRdepth_r1 PRdepth_r2 PRdepth_r3 PRdepth_r4 PRdepth_r5 PRdepth_r1 + PRcycle_r1 PRdepth_r2 + PRcycle_r2 PRdepth_r3 + PRcycle_r3 PRdepth_r4 + PRcycle_r4 PRdepth_r5 + PRcycle_r5 Compute Depth Resource - Update Processor Resource Depths
  • 7. Trace Head Trace Tail Trace Head BB InstrHeight = BB InstrCount Tail = BB number BB SBB InstrHeight = BB instrCount + SBB InstrHeight Tail = SBB Tail SBB InstrHeight BB InstrCount Tail Case 1: BB has no successor Case 2: BB has successor SBB Compute Height Resource - Update TraceBlockInfo
  • 8. ProcResourceCycles (PRKinds = 5) PRcycle_r1 PRcycle_r2 PRcycle_r3 PRcycle_r4 PRcycle_r5 SBB BB ProcResourceHeights (PRKinds = 5) PRheight_r1 PRheight_r2 PRheight_r3 PRheight_r4 PRheight_r5 PRheight_r1 + PRcycle_r1 PRheight_r2 + PRcycle_r2 PRheight_r3 + PRcycle_r3 PRheight_r4 + PRcycle_r4 PRheight_r5 + PRcycle_r5 Compute Height Resource - Update Processor Resource Heights
  • 9. Pick Trace Predecessor BB PBB1 PBB2 PBB3 Trace Head PBB3 InstrDepth PBB2 InstrDepth PBB1 InstrDepth Best Depth = min (PBBn InstrDepth + PBBn InstCount) PBB1 InstrCount PBB2 InstrCount PBB3 InstrCount
  • 10. Pick Trace Successor Trace Tail SBB1 SBB2 SBB3 BB SBB3 InstrHeight SBB2 InstrHeight SBB1 InstrHeight Best Height = min (SBBn InstrHeight)
  • 11. • Inverse post-order traversal of predecessors. • Call pickTracePred() to find the best predecessor. • Compute depth resources • TraceBlockInfo • instruction depth, trace head, etc. • ProcResourceDepths[] • cycles count for each processor resources from trace head to the basic block, does not include cycles in the basic block. • Post-order traversal of successors. • Call pickTraceSucc() to find the best successor. • Compute height resources • TraceBlockInfo • instruction height, trace tail, etc. • ProcResourceHeights[] • cycles count for each processor resources from the basic block to trace tail, including cycles in the basic block. Compute Trace for Basic Block
  • 12. Data Dependency • There are three elements in data dependency structure • Defining MachineInstr • Operand number in defining MachineInstr • Operand number in using MachineInstr • These three elements are used by Target Schedule Model to compute latency between defining and using instructions for operands.
  • 13. Add LiveIn DefMBB: … Reg = … … Trace Tail BB #2 BB #1 Trace Head Add Reg to LiveIns for all successors LiveIns.push_back(Reg) LiveIns.push_back(Reg) LiveIns.push_back(Reg) Reg is a virtual register defined in DefMBB.
  • 14. MIHeightMap & RegUnits … MI: DefOp, UseOp1, UseOp2 … I: DefOp2, DefOp, … … DefOp.Cycle (Height of I) Latency of DefOp (MI, I) Height = Latency + DefOp.Cycle // UseOp2 is a physical register. RegUnits[UseOp2].Cycle = max (RegUnits[UseOp2].Cycle, Height) RegUnits[UseOp2].MI = MI RegUnits[UseOp2[.Op = 2 Trace Tail … DI: UseOp1, … … Data dependency (DI, 0, 1) UseOp1 is virtual register DefOp is physical register Latency of UseOp1 (DI, MI) MIHeightMap.insert (DI, Latency of UseOp1 + Latency of DefOp + DefOp.Cycle)
  • 15. MIHeightMap & RegUnits … MI: DefOp, UseOp1, UseOp2 … I: DefOp2, DefOp, … … DefOp.Cycle (Height of I) Latency of DefOp (MI, I) Height = Latency + DefOp.Cycle // UseOp2 is a physical register. RegUnits[UseOp2].Cycle = max (RegUnits[UseOp2].Cycle, Height) RegUnits[UseOp2].MI = MI RegUnits[UseOp2[.Op = 2 Trace Tail … DI: UseOp1, … … Data dependency (DI, 0, 1) DefOp is physical register Latency of UseOp1 (DI, MI) MIHeightMap.insert (DI, Latency of UseOp1 + Latency of DefOp + DefOp.Cycle) Computed by updatePhysDepsUpwards() UseOp1 is virtual register
  • 16. MIHeightMap & RegUnits … MI: DefOp, UseOp1, UseOp2 … I: DefOp2, DefOp, … … DefOp.Cycle (Height of I) Latency of DefOp (MI, I) Height = Latency + DefOp.Cycle // UseOp2 is a physical register. RegUnits[UseOp2].Cycle = max (RegUnits[UseOp2].Cycle, Height) RegUnits[UseOp2].MI = MI RegUnits[UseOp2[.Op = 2 Trace Tail … DI: UseOp1, … … Data dependency (DI, 0, 1) DefOp is physical register Latency of UseOp1 (DI, MI) MIHeightMap.insert (DI, Latency of UseOp1 + Latency of DefOp + DefOp.Cycle) Computed by getDataDep() UseOp1 is virtual register
  • 17. MIHeightMap & RegUnits … MI: DefOp, UseOp1, UseOp2 … I: DefOp2, DefOp, … … DefOp.Cycle (Height of I) Latency of DefOp (MI, I) Height = Latency + DefOp.Cycle // UseOp2 is a physical register. RegUnits[UseOp2].Cycle = max (RegUnits[UseOp2].Cycle, Height) RegUnits[UseOp2].MI = MI RegUnits[UseOp2[.Op = 2 Trace Tail … DI: UseOp1, … … Data dependency (DI, 0, 1) DefOp is physical register Latency of UseOp1 (DI, MI) MIHeightMap.insert (DI, Latency of UseOp1 + Latency of DefOp + DefOp.Cycle) Computed by pushDepHeight() UseOp1 is virtual register MIHeightMap[MI] or computed by updatePhysDepsUp wards() if MI contains physical registers
  • 18. Compute Instruction Depth BB Trace Head BB #2 BB #1: … UseMI… for all instruction UseMI in BB #1: for all data dependency: Cycle = max (Cycles[DefMI].Depth + Latency (DefMI, UseMI)) Has valid instruction Depth. compute instruction depth from BB #1. Critical path length for basic block is maximum of Cycles[MI].Depth + Cycles[MI].Height for all instructions MI in basic block. … DefMI… data dependency Latency of (DefMI, UseMI) Cycles[DefMI].Depth Cycles[UseMI].Depth = Cycle
  • 19. Compute Instruction Depth BB Trace Head BB #2 BB #1: … UseMI… for all instruction UseMI in BB #1: for all data dependency: Cycle = max (Cycles[DefMI].Depth + Latency (DefMI, UseMI)) Has valid instruction Depth. compute instruction depth from BB #1. Critical path length for basic block is maximum of Cycles[MI].Depth + Cycles[MI].Height for all instructions MI in basic block. … DefMI… data dependency Latency of (DefMI, UseMI) Cycles[DefMI].Depth Cycles[UseMI].Depth = Cycle 1. Get data dependency
  • 20. Compute Instruction Depth BB Trace Head BB #2 BB #1: … UseMI… for all instruction UseMI in BB #1: for all data dependency: Cycle = max (Cycles[DefMI].Depth + Latency (DefMI, UseMI)) Has valid instruction Depth. compute instruction depth from BB #1. Critical path length for basic block is maximum of Cycles[MI].Depth + Cycles[MI].Height for all instructions MI in basic block. … DefMI… data dependency Latency of (DefMI, UseMI) Cycles[DefMI].Depth Cycles[UseMI].Depth = Cycle 2. Calculate UseMI’s cycle
  • 21. Compute Instruction Depth BB Trace Head BB #2 BB #1: … UseMI… for all instruction UseMI in BB #1: for all data dependency: Cycle = max (Cycles[DefMI].Depth + Latency (DefMI, UseMI)) Has valid instruction Depth. compute instruction depth from BB #1. Critical path length for basic block is maximum of Cycles[MI].Depth + Cycles[MI].Height for all instructions MI in basic block. … DefMI… data dependency Latency of (DefMI, UseMI) Cycles[DefMI].Depth Cycles[UseMI].Depth = Cycle 3. Update UseMI’s Depth
  • 22. Compute Instruction Height Trace Tail BB BB #2 BB #1: MI… Has valid instruction Height. Succ compute through the trace blocks in bottom-up order if MI has no physical registers: Cycle = Heights[MI] else Cycle = updatePhysDepsUpwards() update Heights according to data dependency Cycles[MI].Height = Cycle if LiveInReg is virtual register: LiveInReg.Height = Heights[DefMI] if LiveInReg is physical register LiveInReg.Height = RegUnit.Cycle
  • 23. Compute Instruction Height Trace Tail BB BB #2 BB #1: MI… Has valid instruction Height. Succ compute through the trace blocks in bottom-up order if MI has no physical registers: Cycle = Heights[MI] else Cycle = updatePhysDepsUpwards() update Heights according to data dependency Cycles[MI].Height = Cycle if LiveInReg is virtual register: LiveInReg.Height = Heights[DefMI] if LiveInReg is physical register LiveInReg.Height = RegUnit.Cycle 1. Get data dependency
  • 24. Compute Instruction Height Trace Tail BB BB #2 BB #1: MI… Has valid instruction Height. Succ compute through the trace blocks in bottom-up order if MI has no physical registers: Cycle = Heights[MI] else Cycle = updatePhysDepsUpwards() update Heights according to data dependency Cycles[MI].Height = Cycle if LiveInReg is virtual register: LiveInReg.Height = Heights[DefMI] if LiveInReg is physical register LiveInReg.Height = RegUnit.Cycle 2. Compute cycles of MI
  • 25. Compute Instruction Height Trace Tail BB BB #2 BB #1: MI… Has valid instruction Height. Succ compute through the trace blocks in bottom-up order if MI has no physical registers: Cycle = Heights[MI] else Cycle = updatePhysDepsUpwards() update Heights according to data dependency Cycles[MI].Height = Cycle if LiveInReg is virtual register: LiveInReg.Height = Heights[DefMI] if LiveInReg is physical register LiveInReg.Height = RegUnit.Cycle 3. Update Heights[]
  • 26. Compute Instruction Height Trace Tail BB BB #2 BB #1: MI… Has valid instruction Height. Succ compute through the trace blocks in bottom-up order if MI has no physical registers: Cycle = Heights[MI] else Cycle = updatePhysDepsUpwards() update Heights according to data dependency Cycles[MI].Height = Cycle if LiveInReg is virtual register: LiveInReg.Height = Heights[DefMI] if LiveInReg is physical register LiveInReg.Height = RegUnit.Cycle 4. Update MI’s Height
  • 27. Compute Instruction Height Trace Tail BB BB #2 BB #1: MI… Has valid instruction Height. Succ compute through the trace blocks in bottom-up order if MI has no physical registers: Cycle = Heights[MI] else Cycle = updatePhysDepsUpwards() update Heights according to data dependency Cycles[MI].Height = Cycle if LiveInReg is virtual register: LiveInReg.Height = Heights[DefMI] if LiveInReg is physical register LiveInReg.Height = RegUnit.Cycle 5. Update LiveInReg’s Height
  • 28. Compute Cross Block Critical Path BB LIR in BB’s LiveIns … LIR.Reg = … (DefMI) … Len = LIR.Height + Cycles[DefMI].Depth for all LIR in LiveIns, the maximum of Len is critical path length for the basic block BB. LIR.Height: Height of defining instruction Trace Head Cycles[DefMI].Depth: Earliest issue cycle as determined by data dependencies and instruction latencies from the beginning of the trace. Trace Tail LIR.Reg is a virtual register