LPC 2148 ARM MICROCONTROLLER

 ARM started life as part of Acorn computer, and now
designs chips for Apple's iPad.
 1978 - Acorn Computers is established in Cambridge, and
produces computers which are particularly successful in
the UK. Acorn's BBC Micro computer was the most
widely-used computer in school in the 1980s.

 1985 - Acorn Computer Group develops the world's first
commercial RISC processor - enabling a computer system
which uses simpler commands in order to operate faster,
an advance on the early computer systems which were
created using machine code and tried to pack as many
actions into each command as possible.
 1987 - Acorn's ARM processor is the first RISC
processor available in a low-cost PC.

 1990 - ARM is founded as a spin-off from Acorn and
Apple, after the two companies started collaborating on the
ARM processor as part of the development of Apple's new
Newton computer system.
 2007 - About 98pc of the more than 1bn mobile phones
sold each year use at least one ARM processor.
 2008 - The 10 billionth processor chip based on ARM's
designs is shipped.

 ARM stands for Advanced RISC Machines
 An ARM processor is basically any 16/32bit microprocessor
designed and licensed by ARM Ltd, a microprocessor
design company headquartered in England, founded in 1990
by Herman Hauser
 A characteristic feature of ARM processors is their low
electric power consumption, which makes them particularly
suitable for use in portable devices.
 It is one of the most used processors currently on the market

 The ARM is a 32-bit reduced instruction set
computer (RISC).
 It was known as the Advanced RISC Machine,
and before that as the Acorn RISC Machine
 ARM processors made them suitable for low
power applications.
 This has made them dominant in the mobile
and embedded electronics market as relatively
low cost.

ARM7TDMI –S stands for:
ARM - Advanced RISC Machines
 7 - Version number of the architecture
 T - THUMB: 32-bit wide instruction words 16-bit wide
memory
 D - Debug: 2 break points to stop the CPU (both
hardware and software)
 M - Multiplier: enhanced (relative to earlier ARM cores)
32x8 Multiplier.
9

 I: Interface: Embedded ICE macro cell. JTAG- Joint
Test Action Group.
 -S: synthesizable (ie., distributed as RTL rather than
a hardened layout)

 PACKAGE:
 16/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64
package.
 MEMORY:
 40 kB of on-chip static RAM
 512 kB of on-chip flash program memory.
 SPEED:
 128 bit wide interface/accelerator enables high speed 60 MHz
operation.

 In-System / In-Application Programming (ISP/IAP) via on-
chip boot-loader software.
 Single flash sector or full chip erase in 400 ms and
programming of 256 bytes in 1ms.
 USB 2.0 Full Speed compliant Device Controller with 2kB
of endpoint RAM.
 In addition, the LPC2146/8 provides 8kB of on-chip RAM

 ADC:
 Two 10-bit A/D converters(AD0 and AD1) provide a total
of 14 analog inputs
 Conversion times as low as 2.44μs per channel.
 DAC:
 Single 10-bit D/A converter provides variable analog output.

 TIMERS:
 Two 32-bit timers/external event counters
 Each timer with four capture and four compare channels
 PWM unit (six outputs)
 Watchdog timer
 RTC:
 Low power real-time clock with independent power and
dedicated 32 kHz clock input.

 SERIAL INTERFACES:
 I2C-bus:
 Two Fast I2C-bus with 400 kbit/s
 Serial communication:
 Two UARTs (16C550)
 SPI (Serial Peripheral Interface) and SSP(Synchronous Serial
Port) with buffering and variable data length capabilities
 FAST GPIO: Up to 45 of 5 V tolerant fast general purpose I/O
pins in a tiny LQFP64

 INTERRUPTS:
 Vectored interrupt controller with 16 configurable priorities
and vector addresses.
 9 edge or level sensitive external interrupt pins available.
 60 MHz maximum CPU clock available from
programmable on-chip PLL with settling time of 100 μs.

 OSCILLATOR:
 On-chip integrated oscillator operates with an external crystal
in range from 1 MHz to 30 MHz and with an external oscillator
up to 50 MHz
 POWER SAVING MODES:
 Idle mode
 Power-down mode
 CPU operating voltage range of 3.0 V to 3.6 V (3.3 V ± 10
%) with 5 V tolerant I/O pads.

• Industrial control
• Medical systems
• Access control
• Point-of-sale
• Communication gateway
• Embedded soft modem
• General purpose applications

 The 8051 is based on an 8-bit CISC core with
Harvard architecture.
 It's an 8-bit CPU, the program bus is 16 bits
wide
 whereas the data bus is 8 bits wide.

Feature
 ROM
 RAM
 IO PORTS
 Timers
 Serial commn’s
 Interrupts
 Package
Quantity
 4KB
 128 bytes
 4(P0,P1,P2,P3)
 2
 1(UART)
 6
 40 pins

 The ARM is a 32-bit reduced instruction set computer
(RISC) instruction set architecture (ISA) developed by
ARM Holdings
 LPC2141/42/44/46/48 microcontrollers are based on a
16-bit/32-bit ARM7TDMI-S CPU with real-time
emulation and embedded trace support, that combine
microcontroller with embedded high speed flash
memory ranging from 32 kB to 512 kB.

• ROM
• RAM
• IO PORTS
• Timers
• Serial comm
• USB RAM
• 512 KB
• 32 KB
• 2(P0,P1)
• 2(32 bit)
• 2 UART, 2 I2C, 1 SSP
,1 SPI
• 2 KB

• PWM modules
• ADC
• Interrupts
• Package
• DAC
• 6
• 2(14 channels)
• 16
• 64 PIN(LQFP)
• 1

 The ARM7TDMI (ARM7 +Thumb +Debug+ Multiplier+ICE)
processor is a 32-bit RISC CPU designed by ARM.
 The most widely used ARM7 designs, implement the
ARMv4T architecture, but some implement ARMv3
 All these designs use a Von Neumann architecture

 The processor supports both 32-bit and 16-bit
instructions via the ARM and Thumb instruction
sets.
 This generation introduced the Thumb 16-bit
instruction set providing improved code density

 iPod from Apple
 D-Link DSL-604+ Wireless ADSL Router.
 Many automobiles embed ARM7 cores.
 Sirius Satellite Radio receivers
 Most of Nokia's mobile phone range.

 AMBA Bus
 LOCAL Bus
 VPB Bus

The System Control Block includes several system features
and control registers for a number of functions that are
not related to specific peripheral devices. These include:
 Crystal Oscillator
 External Interrupt Inputs
 Miscellaneous System Controls and Status
 Memory Mapping Control
 PLL
 Power Control
 Reset
 VPB Divider
 Wakeup Timer
Each type of function has its own register(s) if any are
required and unneeded bits are defined as reserved in
order to allow future expansion.

 While an input signal of 50-50 duty cycle within a
frequency range from 1 MHz to 50 MHz can be used by
the LPC2141/2/4/6/8 if supplied to its input XTAL1 pin.
 This microcontroller’s onboard oscillator circuit supports
external crystals in the range of 1 MHz to 30 MHz only.
If the on-chip PLL system or the boot-loader is used, the
input clock frequency is limited to an exclusive range of
10 MHz to 25 MHz.

 The oscillator output frequency is called FOSC
 and the ARM processor clock frequency is referred
to as CCLK for purposes of rate equations, etc..
 FOSC and CCLK are the same value unless the PLL
is running and connected.

 The onboard oscillator in the LPC2141/2/4/6/8 can
operate in one of two modes:
 Slave mode
 oscillation mode.
 In slave mode the input clock signal should be
coupled by means of a capacitor of 100 pF with an
amplitude of at least 200mVrms.
 The X2 pin in this configuration can be left not
connected. If slave mode is selected, the FOSC signal
of 50-50 duty cycle can range from 1 MHz to 50 MHz

 Since the feedback resistance is integrated on chip, only a
crystal and the capacitances CX1 and CX2 need to be
connected externally in case of
fundamental mode oscillation (the fundamental frequency
is represented by L, CL and RS).
 Capacitance CP, represents the parallel package
capacitance and should not be larger than 7 pF.
 Parameters FC, CL, RS and CP are supplied by the crystal
manufacturer.
 Choosing an oscillation mode as an on-board oscillator
mode of operation limits FOSC clock selection to 1 MHz to
30 MHz.

 There are two PLL modules in the
LPC2141/2/4/6/8 microcontroller.
 The PLL0 is used to generate the CCLK clock
(system clock) while the PLL1 has to supply the
clock for the USB at the fixed rate of 48 MHz.
 Structurally these two PLLs are identical with
exception of the PLL interrupt capabilities reserved
only for the PLL0.

Lpc 2144/6//8 consists 45 GPIO functionality in is 2
port which as
1. Port0 (P0.0 to P0.31)- 24,26,27 are invisible pins,
remaining 29 are visible i/o pins.
2. Port1 (P1.16 to P0.31)- 16 pins are visible and 16
pins are invisible(P1.0-P1.15)

It consist of 19 different peripherals such as
FUNCTION PIN TYPE & DESCRIPTION
D+ 10 INPUT/OUTPUT(USB bidirectional D+ line)
D- 11 INPUT/OUTPUT(USB bidirectional D- line)
XTAL1 62
XTAL2 61
RTXC1 3 INPUT(Input to the RTC oscillator circuit)
RTXC2 5 OUTPUT(output to the RTC oscillator circuit)
VSS 6, 18 ,25,42,50
VSSA 52 INPUT(Analog Ground: 0 V reference)
VDD 23, 43, 51 (power supply)

 VDDA 7 INPUT(analog power supply)
 VREF 63 INPUT(A/D Converter Reference)
 VBAT 49 INPUT(RTC power supply)

 Pin selection register are used to select the different
functionalities of LPC2148 i/o pins.
 PINSEL0 Pin function select
 Read/Write 0x0000 0000 (P0.0-P0.15)
 Read/Write 0x0000 0000 (P0.16-P0.31)
 Read/Write 0x0000 0000 (P1.16-P1.31)

(Pin of
Select Port Pin sélection Function
Résister) line
 1:0 P0.0 00 GPIO Port 0.0
01 TXD (UART0)
10 PWM1
11 Reserved
 3:2 P0.1 00 GPIO Port 0.1
01 RxD (UART0)
10 PWM3
11 EINT0

 5:4 P0.2 00 GPIO Port 0.2
01 SCL0 (I2C0)
10 Capture 0.0
(Timer 0)
11 Reserved
 7:6 P0.3 00 GPIO Port 0.3
01 SDA0 (I2C0)
10 Match 0.0 (Timer
0)
11 EINT1

 9:8 P0.4 00 GPIO Port 0.4 0
01 SCK0 (SPI0)
10 Capture 0.1
(Timer 0)
11 AD0.6
 11:10 P0.5 00 GPIO Port 0.5 0
01 MISO0 (SPI0)
10 Match 0.1 (Timer
0)
11 AD0.7

 13:12 P0.6 00 GPIO Port 0.6 0
01 MOSI0 (SPI0)
10 Capture 0.2
(Timer
11 Reserved[1][2]
or AD1.0[3]
 15:14 P0.7 00 GPIO Port 0.7
01 SSEL0 (SPI0)
10 PWM2
11 EINT2

 17:16 P0.8 00 GPIO Port 0.8
01 TXD UART1
10 PWM4
11
Reserved[1][2]
or AD1.1[3]
 19:18 P0.9 00 GPIO Port 0.9
01 RxD (UART1)
10 PWM6
11 EINT3

 21:20 P0.10 00 GPIO Port 0.10
01 Reserved[1][2] or RTS
(UART1)[3]
10 Capture 1.0 (Timer 1)
11 Reserved[1][2]
orAD1.2[3]
 23:22 P0.11 00 GPIO Port 0.11
01 Reserved[1][2] or CTS
(UART1)[3]
10 Capture 1.1 (Timer 1)
11 SCL1 (I2C1)

 25:24 P0.12 00 GPIO Port 0.12 0
01 Reserved[1][2] or
DSR (UART1)[3]
10 Match 1.0 (Timer
1)
11 Reserved[1][2]
or AD1.3[3]
 27:26 P0.13 00 GPIO Port 0.13 0
DTR (UART1)[3]
10 Match 1.1 (Timer
1)
11 Reserved[1][2]
orAD1.4[3]

 29:28 P0.14 00 GPIO Port 0.14 0
DCD (UART1)[3]
10 EINT1
11 SDA1 (I2C1)
 31:30 P0.15 00 GPIO Port 0.15 0
RI (UART1)[3]
10 EINT2
11 Reserved[1][2]
orAD1.5[3]

 29:28 P0.14 00 GPIO Port 0.14 0
DCD (UART1)[3]
10 EINT1
11 SDA1 (I2C1)
 31:30 P0.15 00 GPIO Port 0.15 0
01 Reserved[1][2]
or RI
(UART1)[3]
10 EINT2
11 Reserved[1][2]
orAD1.5[3]

 1:0 P0.16 00 GPIO Port 0.16 0
01 EINT0
10 Match 0.2 (Timer
0)
11 Capture 0.2
(Timer 0)
 3:2 P0.17 00 GPIO Port 0.15 0
01 Capture 1.2
(Timer 1)
10 SCK1 (SSP)
11 Match 1.2 (Timer
1)

 5:4 P0.18 00 GPIO Port 0.18 0
01 Capture 1.3
(Timer 1)
10 Match 0.2 (Timer
0)
11 MISO1 (SSP)
 7:6 P0.19 00 GPIO Port
0.19 0
01 Match 1.2
(Timer 1)
10 MOSI1 (SSP)
11 Capture 1.2
(Timer 1)

 9:8 P0.20 00 GPIO Port 0.20 0
01 Match 1.3 (Timer
1)
10 SSEL1 (SSP)
11 EINT3
 11:10 P0.21 00 GPIO Port 0.21 0
01 PWM5
10 Reserved[1][2]
or
AD1.6[3]
11 Capture 1.3
(Timer 1)

 13:12 P0.22 00 GPIO Port 0.22 0
AD1.7[3]
10 Capture
0.0 (Timer 0)
11 Match 0.0
(Timer 0)
 15:14 P0.23 00 GPIO Port 0.23 0
01 VBUS
10 Reserved
11 Reserved

 17:16 P0.24 00 Reserved
01 Reserved
10 Reserved
11 Reserved
 19:18 P0.25 00 GPIO Port 0.25 0
01 AD0.4
10 Reserved[1] or
Aout(DAC)[2][3]
11 Reserved

 21:20 P0.26 00 Reserved
01 Reserved
10 Reserved
11 Reserved
 23:22 P0.27 00 Reserved
01 Reserved
10 Reserved
11 Reserved

 25:24 P0.28 00 GPIO Port 0.28
01 AD0.1
10 Capture 0.2
(Timer 0)
11 Match 0.2 (Timer
0)
 27:26 P0.29 00 GPIO Port 0.29
01 AD0.2
10 Capture 0.3
(Timer 0)
11 Match 0.3 (Timer
0)

 29:28 P0.30 00 GPIO Port 0.30
01 AD0.3
10 EINT3
11 Capture 0.0
(Timer 0)
 31:30 P0.31 00 GPO Port only
01 UP_LED
10 CONNECT
11 Reserved

 General purpose I/O
 Driving LEDs, or other indicators
 Controlling off-chip devices
 Sensing digital inputs

 IODIR Register is used to configure the i/o
pins, either input and output pins
 IODIR is a 32-pin register.
 IODIRx=0x00000000-i/p config.
 IODIRx=0xffffffff-o/p config.

 This register provides the value of port pins that are
configured to perform only digital functions.
 IOPIN register is used to read the current state of
every GPIO pin

 This register is used to produce a HIGH level output
at the port pins configured as GPIO in an OUTPUT
mode.
 Writing 1 produces a HIGH level at the corresponding
port pins.
 Writing 0 has no effect.

 This register is used to produce a LOW level output
at port pins configured as GPIO in an OUTPUT
mode.
 Writing 1 produces a LOW level at the
corresponding port pin and clears the
corresponding bit in the IOSET register.
 Writing 0 has no effect.

#include<LPC214X.h>
void delay(unsigned int);
int main()
{
IODIR0=0X00000001;
while(1)
{
IOSET0=0X00000001;
delay(20);
IOCLR0=0X00000001;
delay(20);
}
}
void delay(unsigned int i)
{
int j,k;
for(j=0;j<i;j++)
for(k=0;k<1275;k++);
}

#include<LPC214X.h>
int main()
{
IODIR0=0X000000ff;
while(1)
{
IOSET0=0X000000ff;
delay(20);
IOCLR0=0X0000000ff;
delay(20);
}
}
{
int j,k;
for(j=0;j<i;j++)
for(k=0;k<1275;k++);
}

#include<LPC214X.h>
int main()
{
IODIR0=0X000000ff;
while(1)
{
IOSET0=0X000000aa;
IOCLR0=0X00000055;
delay(20);
IOSET0=0X00000055;
IOCLR0=0X000000AA;
delay(20);
}
}
{
int j,k;
for(j=0;j<i;j++)
for(k=0;k<1275;k++);
}

 16 byte Receive and Transmit FIFOs
 Receiver FIFO trigger points at 1, 4, 8, and 14 bytes.
 Built-in fractional baud rate generator with auto
bauding capabilities.
 Mechanism that enables software and hardware flow
control implementation

 U0FCR//FIFO CONTROL REG
 U0LCR //LINE CONTROL REG HIGH PULSE
 U0DLL //BAUD RATE
 U0DLM //BAUD RATE
 U0LCR //LINE CONTROL REG LOW PULSE

 UART1 is identical to UART0, with the addition of a
modem interface.
 16 byte Receive and Transmit FIFOs.
 Register locations conform to ‘550 industry standard.
 Receiver FIFO trigger points at 1, 4, 8, and 14 bytes.
 Built-in fractional baud rate generator with autobauding
capabilities.
 Mechanism that enables software and hardware flow
control implementation.
 Standard modem interface signals included with flow
control (auto-CTS/RTS) fully
 supported in hardware (LPC2144/6/8 only).

 The U1RBR is the top byte of the UART1 RX FIFO.
 The top byte of the RX FIFO contains
 the oldest character received and can be read via the bus interface.
 The LSB (bit 0) represents the “oldest” received data bit. If the
character received is less than 8 bits, the unused MSBs are padded
with zeroes.
 The Divisor Latch Access Bit (DLAB) in U1LCR must be zero in
order to access the U1RBR. The U1RBR is always Read Only.

 The U1THR is the top byte of the UART1 TX FIFO.
 The top byte is the newest character in the TX FIFO
and can be written via the bus interface.
 The LSB represents the first bit to transmit.
 The Divisor Latch Access Bit (DLAB) in U1LCR
must be zero in order to access the U1THR.
 The U1THR is always Write Only.

 The UART1 Divisor Latch is part of the UART1 Fractional Baud Rate
Generator and holds the value used to divide the clock supplied by the
fractional prescaler in order to produce the baud rate clock, which must
be 16x the desired baud rate.
 The U1DLL and U1DLM registers together form a 16 bit divisor where
U1DLL contains the lower 8 bits
 of the divisor and U1DLM contains the higher 8 bits of the divisor.
 A 0x0000 value is treated like a 0x0001 value as division by zero is not
allowed.
 The Divisor Latch Access Bit (DLAB) in U1LCR must be one in order
to access the UART1 Divisor Latches.

 The UART1 Fractional Divider Register (U1FDR)
controls the clock pre-scaler for the baud rate
generation and can be read and written at user’s
discretion. This pre-scaler takes the VPB clock and
generates an output clock per specified fractional
requirements.

Parallel transmission:
Data is sent 8 bits (byte) at a time over 8 data lines.
A few handshaking lines may be needed. One uses a 25-pin
D-shell connector and cable(DB-25 or equivalent)
Serial transmission:
Data is sent one bit at a time over one data line. In theory and
principle one needs only two lines for data, one for the signal
and the other for ground. A few clock and handshaking lines
are needed and in many PCs a 9-pin connector is used.

Asynchronous
Synchronous
Transfer:
Simplex
Half duplex
Full duplex

UART means Universal Asynchronous Receiver and
Transmitter
8051 have single UART
In LPC2148 have two UART

UART0 pin description
Pin Type Description
RXD0 Input Serial Input. Serial receive data.
TXD0 Output Serial Output. Serial transmit data.

 U0FCR-FIFO CONTROL REG
• 8-BIT Byte Addressable reg
• This reg is used to enable TX & RX FIFO
functionalities
• U0FCR=0x07 is like SCON reg

 U0LCR- Line Control Reg
• 8-BIT byte addressable reg
• Line control reg is used to select the length of char
• LSB two bits are char length selection bits.
 0 0 – 5(xxx00000)
 0 1 – 6(xx000000)
 1 0 – 7(x0000000)
 1 1 – 8(00000000)

DLAB(Divisor Latch Buffer)
 one high-low pulse across DLAB bit indicates baud
rate is successfully loaded.
 DLAB=1 baud rate is loading
 DLAB=0 After loading baud rate DLAB must be zero.
U0LCR=0X83
BAUD RATE
U0CLR=0X03

 Divisor Latch Reg
• DLR is 16-bit reg
• Used to load baud rate
• As the baud rate is 8-bit value, divide DLR
into two parts
• DLM & DLL(8-bit each)
• For 9600 baud rate
• U0DLL=0x63(12mhz)
• U0DLM=0x00

 U0THR(Transmit hold reg)
• 8-bit byte addressable reg
• Data can be loading to U0THR, whenever
transmitting data
• U0THR=‘A’----like SBUF
• THR buffer reg is used only for transmitting

 U0RBR(UART0 Receive buffer reg)
 8-bit byte addressable reg
 Data can be loading into U0RBR, whenever
receiving data.
 a=U0RBR----like SBUF

 U0LSR(UART0 line status reg)
 8-bit byte addressable reg
 Consists of diff flag bits… TI interrupt & RI interrupt
flag bit
 0th bit of LSR is RI flag bit
 6th bit of LSR is TI flag bit
 Monitoring TI bit syntax
 While(!(U0LSR&0x40));
 Monitoring RI bit syntax
 While(!(U0LSR&0x10));

#include<LPC214X.H>
void sercon(void);
int main()
{
sercon();
while(1)
{
U0THR='A';
while(!(U0LSR&0X40));
}
}
void sercon(void)
{
PINSEL0=0X00000005;
U0LCR=0X83;
U0DLL=0X061;
U0LCR=0X03;
}

#include<LPC214X.H>
void sercon(void);
int main()
{
unsigned char X;
sercon();
while(1)
{
X=U0RBR;
U0THR=X;
}
}

void sercon(void)
{
PINSEL0=0X00000005;
U0LCR=0X83;
U0DLL=0X061;
U0LCR=0X03;
}

RS:REGISTER SELECT
 there are two registers inside the LCD.
 Command Register and Data Register.
 RS pin is used for their selection.
 if RS=0, command register is selected.
 if RS=1, data register is selected.

R/W: READ/WRITE
 Allows user to read the information from the LCD and write the
information to the LCD.
R/W=1 when reading
R/W=0, when writing
E: ENABLE
 used by the LCD to latch the information from its data lines.
 a high to low pulse must be applied to this pin to receive data.
 this pulse must be 450ns wide.

VCC: +5V POWER SUPPLY
VSS: GROUND
VEE: TO CONTROL LCD CONTRAST.
D0-D7: 8 Bit data pins used to send
information to the LCD or read the
contents of the LCD’s internal
registers.

0x38: 2 lines and 5x7 matrix
0x01: clear display screen
0x0E: display on, cursor blinking
0x06: increment cursor(shift cursor to right)
0x80: force cursor to beginning of 1st line
0xC0: force cursor to beginning of 2nd line

• 1.Make R/W low
• 2.Make RS=0 ;if data byte is command
RS=1 ;if data byte is data (ASCII value)
• 3.Place data byte on data register
• 4.Pulse E (HIGH to LOW)
• 5.Repeat the steps to send another data byte

#include<LPC214X.H>
#define rs 0x00010000;
#define en 0x00020000;
#define d1 0x00040000;
#define d2 0x00080000;
#define d3 0x00100000;
#define d4 0x00200000;
void lcd_cmd(unsigned char);
void lcd_dat(unsigned char);
void disp_str(unsigned char * );

int main()
{
IODIR0=0X003F0000;
while(1)
{
lcd_cmd(0x28);
delay(20);
lcd_cmd(0x01);
delay(20);
lcd_cmd(0x0e);
delay(20);
lcd_cmd(0x80);
delay(20);
lcd_cmd(0x06);
delay(20);
lcd_dat('a');
delay(20);
disp_str("hello");
}
}

void lcd_cmd(unsigned char x)
{
unsigned char y,z;
y=(x>>4)&0x0f;
IOSET0=y<<18;
IOCLR0=rs;
IOSET0=en;
delay(20);
IOCLR0=en;
IOCLR0=0x003f0000;
z=x&0x0f;
IOSET0=z<<18;
IOCLR0=rs;
IOSET0=en;
delay(20);
IOCLR0=en;
}

void lcd dat(unsigned char value)
{
unsigned char a,b;
a=(value>>4)&0x0f;
IOSET0=a<<18;
IOSET0=rs;
IOSET0=en;
delay(20);
IOCLR0=en;
IOCLR0=0x003f0000;
b=value&0x0f;
IOSET0=b<<18;
IOSET0=rs;
IOSET0=en;
delay(20);
IOCLR0=en;
}

void disp_str(unsigned char *p)
{
while(*p!='0')
{
lcd_dat(*p);
*p++;
}
}
void delay(unsigned int j)
{
int k,l;
for(k=0;k<j;k++)
for(l=0;l<1275;l++);
}

LPC 2148 ARM MICROCONTROLLER

In this document