This document describes the design of an IEEE 754 single precision floating point multiplier. It discusses how floating point numbers are represented in binary format according to the IEEE 754 standard. The designed multiplier handles overflow and underflow cases and implements floating point multiplication by multiplying significands, adding exponents, determining the sign, and normalizing the result. Simulation results show the multiplier works as intended according to the IEEE 754 standard.

1. DESIGN OF HIGH SPEED
IEEE-754 SINGLE PRECISION
FLOATING POINT MULTIPLER

2. ABSTRACT
 A fast and energy-efficient floating point unit is always needed in electronics
industry especially in DSP, image processing and as arithmetic unit in
microprocessors.
 we present the design of an IEEE 754 single precision floating point multiplier.
Floating point numbers are one possible way of representing real numbers in
binary format.
 The IEEE 754 standard presents two different floating point formats, Binary
interchange format and Decimal interchange format. In this project we focus
on single precision normalized binary interchange format.
 The multiplier design handles the overflow and underflow cases. Rounding is
not implemented to give more precision when using the multiplier in a
Multiply and Accumulate (MAC) unit.

3. INTRODUCTION
 A standard notation enables easy exchange of data between
machines and simplifies hardware algorithms.
 In IEEE 754 standards, the floating-point numbers is represented by
three field.
31 30 22 0
 Value of a floating-point number is
(–1) Sign × (1.Significant) × 2(exponent bias).
where bias is equal to 127.
Sign
(1)
Exponent
(8-bits)
Significant
(23-bits)

4. OUTLINE
• Proposed System
• Existing System
• Implementation of floating point multiplication
• HDL implementation of top multiplier
• Simulation Results
• Conclusion
• Future Scope

5. PROPOSED SYSTEM
 It can be designed for 32 bit operands to enhance precision.
 Booth multiplier is used for mantissa multiplication.
 Booth can further increase the efficiency of the FPU in terms of
speed.
 It is based on issues such as areas, delay and power consumption

6. EXISTING SYSTEM
 The designed arithmetic unit operates on 32 bit operands.
 Vedic multiplier is used for multiplication.
 Area, delay and power consumption is reduced
 The above elements are reduced so that speed can be improved.

7. Floating-Point Multiplication:
To multiply two floating point numbers the following is done:
 Multiplying the significand; i.e. (1.M1*1.M2)
 Placing the decimal point in the result
 Adding the exponents; i.e. (E1 + E2 – Bias)
 Obtaing the sign; i.e. s1 xor s2
 Normalizing the result; i.e. obtaining 1 at the MSB of the results’
significand,
 Rounding the result to fit in the available bits
 Checking for underflow/overflow occurrence.
IMPLEMENTATION OF FLOATING
POINT MULTIPLICATION

8. Considering the random floating point numbers,
Inputs: a = 19.2; b = 66.6
Output: result = 1278.72
Here we have taken two positive 32-bit Floating point numbers.
A = 0 10000011 0011 = 19.2
B = 0 10000101 0000 = 66.6
Exp_add_out_temp: It represent the result of exponent bit that is
10000011+10000101 = 100001000
The exponent representing the two numbers is already shifted/biased by the
bias value (127) and is not the true exponent; i.e. EA = EA-true + bias and EB
= EB-true + bias And EA+ EB = EA-true + EB-true + 2 bias.

9.  So we should subtract the bias from the resultant exponent otherwise the
bias will be added twice.
100001000
- 01111111
10001001
 Mul_out_temp: It represent the result of Mantissa bit
1.0011 x 1.0000 = 100110000
 Top_Multiplier_out_temp: It represents the overall the result of two
floating point multiplier. That is a combination of Sign bit, Exponent and
Mantissa result.
0 10001001 00110000000000000000000

10. HARDWARE OF FLOATING
POINT MULTIPLIER :
Fig: Implementation of Floating Point Multiplier

11. Block Diagram:

12. Sign bit calculation:
 The main component of Sign calculator is XOR gate. If any one of the
numbers is negative then result will be negative. The result will be positive
if two numbers are having same sign
Unsigned Adder (for exponent addition):
 This sub-block adds the exponents of the two floating point numbers and
the Bias (127) is subtracted from the result to get true result i.e. EA + EB –
bias. To perform addition of two 8-bit exponents, an 8-bit ripple carry
adder (RCA) is used. The Bias is subtracted using an array of ripple
borrow subtractors.
Fig: Ripple Carry Adder

13. Multiplier for Unsigned Data:
 This unit is used to multiply the two unsigned significand
numbers and it places the decimal point in the multiplied
product.
 The result of this significand multiplication will be called the
intermediate product (IP). Multiplication is to be carried out so
as not to affect the whole multiplier’s performance.
 In shift and add multiplier, the carry bits are passed diagonally
downwards. Partial products are generated by AND the inputs
of two numbers and passing them to the appropriate adder.

14. Normalizer:
 The result of the significand multiplication (intermediate
product) must be normalized to have a leading ‘1’ just to the
left of the decimal point. The shift operation is done using
combinational shift logic made by multiplexers.

15. Underflow /Overflow Detection:
 Overflow/underflow means that the result’s exponent is too large/small to be
represented in the exponent field.
 When an overflow occurs an overflow flag signal goes high and the result
turns to ±Infinity.
 When an underflow occurs an underflow flag signal goes high and the result
turns to ±Zero.
 Assume that E1 and E2 are the exponents of the two numbers A and B
respectively; the result’s exponent is calculated by
ERESULT = E1 + E2 - 127

16.  Table summarizes the ERESULT different values and the effect of
normalization on it.
 E1 and E2 can have the values from 1 to 254; resulting in ERESULT having
values from -125 (2-127) to 381 (508-127); but for normalized numbers,
ERESULT can only have the values from 1 to 254.
Fig. Normalization Effect On Result’s Exponent And Overflow/Underflow
Detection

17. SIMULATION RESULTS OF TOP
MULTIPLIER:
RTL Schematic of top multiplier:

18. TECHNOLOGY SCHEMATIC:

19. SIMULATION OUTPUT RESULT :

20. CONCLUSION:
 Single Precision Floating Point Multiplier unit has been designed to using
fast adder and fast multipliers. IEEE 754 standard based floating point
representation has been used.
 With the remarkable progress in the very large scale integration (VLSI)
circuit technology, many complex circuits, unthinkable yesterday have
become easily realizable today.
 Algorithms that seemed impossible to implement now have attractive
implementation possibilities for the future.

21. FUTURE SCOPE:
 The designed arithmetic unit operates on 32-bit operands. It can be designed
for 64-bit operands to enhance precision. It can be extended to have more
mathematical operations like addition, subtraction, division, square root,
trigonometric, logarithmic and exponential functions.
 A few researchers have shown that there is a considerable improvement in
the delay by using 4:2, 5:2, 6:2, 7:2 compressors for Wallace tree as
compared to Vedic multiplier.
 It is therefore required to further research on the efficiency of the various
Wallace tree design approaches for mantissa multiplication based on issues
such as area, delay and power consumption.