- 1. Sequential circuits are two types • Synchronous sequential circuits. In synchronous sequential circuits the clock is common to all the flip flops. • Asynchronous sequential circuits In asynchronous sequential circuits the clock is not common for all the flip flops. The procedure for designing synchronous sequential circuits 1. From the word description and specifications of the desired operation, derive a state diagram for the circuit. 2. Reduce the number of states if necessary. 3. Assign binary values to the states. 4. Obtain the binary-coded state table. 5. Choose the type of flip-flops to be used. 6. Derive the simplified flip-flop input equations and output equations. 7. Draw the logic diagram.
- 2. Design a sequence detector which produce output ‘1’ after receiving a 4-bit sequence “1111” otherwise ‘0’. State diagram A state diagram is a graphical representation of given problem. States are represented with circles, state transitions are represented with arcs and inputs/outputs on them. Here states are S0, S1, S2, S3 input x, output y, state binary variables are A, B. Binary values to the states are S0 : 00, S1: 01, S2 : 10 and S3: 11 Moore type state diagram
- 3. Synthesis or Design using D Flip-Flops For four states two flip-flops are required, if they are DA and DB
- 4. Logic diagram of sequence detector
- 5. Registers A 4-bit Register A register is a group of flip‐flops, each one of which shares a common clock and is capable of storing one bit of information. An n‐bit register consists of a group of n flip‐flops capable of storing n bits of binary information.
- 6. A 4-bit register with parallel load If Load = ‘0’, no change in the content of register. If Load = ‘1’ it loads the given input in the register.
- 7. Shift registers A register capable of shifting the binary information held in each cell to its neighboring cell, in a selected direction, is called a shift register. Serial Input Serial Output (SISO) shift register (Shift right) SISO (Shift left)
- 8. 4-bit Serial Input Parallel Output (SIPO) shift register
- 9. s1 s0 Operation 0 0 No change 0 1 Right shift (with serial input for shift- right) 1 0 Left shift (with serial input for shift- left) 1 1 parallel load Universal Shift Register A Universal Shift Register performs four operations based on the selection 1. No change, 2. shift right, 3. shift left and 4. parallel load. 4x1 muxs are used for operation selection.
- 10. Applications of Shift registers Shift Registers are used for data storage. Movement of data. Arithmetic and logical operations. Multiplication and division with shift operations.
- 11. Counters A Digital system that produce a sequence in increasing or decreasing order is called counter. A counter which produce increasing sequence is called upcounter and which produce decreasing sequence is called downcounter A counter that follows the binary number sequence is called a binary counter. Counting sequence of a 3-bit binary up counter is “000”, “001”, “010”, “011”, “100”, “101”, “110”, “111”, Counting sequence of a 3-bit binary down counter is “111”, “110”, “101”, “100”, “011”, “010”, “001”, “000”, Counters are two types: Ripple counters (asynchronous counters) and synchronous counters.
- 12. Ripple counters Logic diagram of 4-bit binary ripple counter Timing diagram of 4-bit binary ripple counter
- 13. BCD Ripple Counter or Decimal Ripple Counter Logic diagram of a BCD counter State diagram of a BCD counter After “1001” it should return to “0000” Q1 changes state after each clock pulse. Q2 complements every time Q1 goes from 1 to 0, as long as Q8 = 0. When Q8 becomes 1, Q2 remains at 0. Q4 complements every time Q2 goes from 1 to 0. Q8 remains at 0 as long as Q2 or Q4 is 0. When both Q2 and Q4 become 1, Q8 complements when Q1 goes from 1 to 0. Q8 is cleared on the next transition of Q1. Note that the output of Q1 is applied to the C inputs of both Q2 and Q8 and the output of Q2 is applied to the C input of Q4. The J and K inputs are connected either to a permanent 1 signal or to outputs of other flip‐flops.
- 14. Timing diagram of BCD counter
- 17. 4-bit up-down synchronous counter If up = ‘1’ and down = ‘X’ it performs up counting. The four bit up counter counts from “0000” to “1111” by incrementing ‘1’ for each clock and then return to “0000”. If up = ‘0’ and down = ‘1’ it performs down counting. The four bit down counter counts from “1111” to “0000” and then return to “1111”. If up = ‘0’ and down = ‘0’ no change in the output.
- 19. Logic diagram Synchronous BCD counter
- 20. Ring counter with initial value “1000” The counter sequence is “1000”, “0100”, “0010”, “0001”, “1000”, An n-bit ring counter consists of n counting states Ring counter
- 21. Johnson counter or Switch-tail ring counter or Twisted ring counter An n-bit twisted ring counter consists of 2n counting states
- 22. Counter with unused States A divide‐by‐ N counter (also known as a modulo‐ N counter) is a counter that goes through a repeated sequence of N states. A circuit with n flip‐flops has 2n binary states. There are occasions when a sequential circuit uses fewer than this maximum possible number of states. States that are not used are called as unused states. Mod-6 counter A mod-6 or divide by 6 counter consists of 6 states. Qn Qn+1 J K 0 0 0 X 0 1 1 X 1 0 X 1 1 1 X 0