Design and Implementation of a Five-Stage Pipelined 32-bit RISC-V Processor Using Verilog

Design and Implementation of a Five-Stage Pipelined 32-bit RISC-V Processor Using Verilog

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  B. Tech ECEPROJECT-1 Review-1 Design and implementation of five stage pipelined RISC-V processor using Verilog Team Members Details Faculty Guide RITHISH KUMAR R S:- 21BEC2521 Dr. SAKTHIVEL R SAKTHIVEL B:- 21BEC2165 Department:- SENSE
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  CURRENT STATUS ANDMOTIVATION Current status: We have implemented a five staged 32-bit RISC V, which includes six instruction set types : R-type ,I-type, B-type, J-type , L-type and S-type. This design features a five-stage pipeline consisting of instruction fetch, instruction decode, instruction execute, memory access, write back stages. Motivation:
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  IDENTIFICATION OF GAPSIN RISC V: Software Ecosystem: Less mature compared to ARM and x86, with fewer tools, libraries, and applications. Hardware Maturity: RISC-V hardware implementations are still developing in terms of performance and efficiency. ISA Compliance: Ensuring that RISC-V cores strictly follow the ISA specifications is challenging, requiring thorough verification of instructions and registers. Tool Gaps: Limited availability and maturity of simulators, verification methods, and development tools.
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  Software Used: The primarydevelopment was done using Modelsim , and Quartus prime was used to synthesis the output Modelsim: Primary used for simulating HDL designs (VHDL , Verilog). It helps developers Verify and debug their hardware logic by providing detailed waveform outputs and Simulation logs. Quartus Prime: This is used for synthesis, compilation, and programming of designs onto FPGA hardware. It takes the HDL design and synthesizes it into a hardware circuit that Can be mapped onto a programmable device. Programming language used: Verilog
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  OBJECTIVE Our primary objectiveis to design a 32- bit RISC V Processor using Verilog for hardware description and to use Universal Verification Methodology(UVM) for comprehensive verification. The key goals are: 1 Accurate Processor Design 2 Efficiency and Performance 3 Comprehensive Verification with UVM
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  METHODOLOGY Architecture of RV32Iprocessor:
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  ISA (Instruction SetArchitecture): funct7 rs2 rs1 funct3 rd opcode R-Type Instr[31:25] Instr[24:20] Instr[19:15] Instr[14:12] Instr[11:7] Instr[6:0] Imm[11:0] rs1 funct3 rd opcode I-Type Imm[11:5] rs2 rs1 funct3 Imm[4:0] opcode S-Type Imm[12] Imm[10:5] rs2 rs1 funct3 Imm[4:1] Imm[11] opcode B-Type imm[31:12] rd opcode U-Type Imm[20] Imm[10:1] Imm[11] Imm[19:12] rd opcode J-Type Type Instruction Field Field Name Bit Range Description Width (bits) Opcode [6:0] Determine the type of instruction (eg:- arithmetic , load , store , branch..) 7 Rd [11:7] Destination register 5 Funct3 [14:12] Determine the operation variant within the instruction type (eg:- addition , subtract..) 3 Rs1 [19:15] Source register 1 5 Rs2 [24:20] Source register 2 5 funct7 [31:25] Additional operation information such as whether the operation is signed or unsigned 7
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  Operation Implementation ADD RegFile[rd]= RegFile[rs2]+RegFile[rs1]; SUB RegFile[rd] = RegFile[rs1]-RegFile[rs2]; SLL RegFile[rd] = RegFile[rs1] << (RegFile[rs2] & 0x1F); SLT RegFile[rd] = ( (signed long)RegFile[rs1] < (signed long)RegFile[rs2] ) ? 1 : 0; SLTU RegFile[rd] = (RegFile[rs1]<RegFile[rs2]) ? 1 : 0; XOR RegFile[rd] = RegFile[rs1] ^ RegFile[rs2]; SRL RegFile[rd] = RegFile[rs1] ^ RegFile[rs2]; SRA RegFile[rd] = RegFile[rs1] >> (RegFile[rs2] & 0x1F); OR RegFile[rd] = RegFile[rs1] | RegFile[rs2]; AND RegFile[rd] = RegFile[rs1] & RegFile[rs2]; R Type Instruction Explained :
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  S ,J andL Type Instruction Explained : Operation Implementation ADDI RegFile[rd] = Immediate_Value+RegFile[rs1]; SLLI RegFile[rd] = RegFile[rs1] << (Immediate_Value ); SLTI RegFile[rd] = ( (signed long)RegFile[rs1] < (signedlong)Immediate_Value ) ? 1 : 0; SLTIU RegFile[rd] = (RegFile[rs1]<Immediate_Value) ? 1 : 0; XORI RegFile[rd] = RegFile[rs1] ^ Immediate_Value; SRLI RegFile[rd] = RegFile[rs1] >> (Immediate_Value ); SRAI RegFile[rd] = RegFile[rs1] >>>(Immediate_Value ); ORI RegFile[rd] = RegFile[rs1] | Immediate_value; ANDI RegFile[rd] = RegFile[rs1] & Immediate_Value; I-Type Instruction Explained: Operation Implementation Instruction Type SW Data_Memory[(Immediate_Value + RegFile[rs1])] = RegFile[rs2] ; S Type JAL RegFile[rd] = PC + 0x4; PC = Immediate_Value + PC ; J Type LW RegFile[rd] = Data_Memory[Immediate_Value + RegFile[rs1]] ; L Type
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  Operation Implementation BEQ if(RegFile[rs1]== RegFile[rs2]) { PC = Immediate_Value + PC ; } BNE if(RegFile[rs1] != RegFile[rs2]) { PC = Immediate_Value + PC ; } BLTU if(RegFile[rs1] < RegFile[rs2]) { PC = Immediate_Value + PC ;} BGTU if(RegFile[rs1] >= RegFile[rs2]) { PC = Immediate_Value + PC ; } B - Type Instruction Explained
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  Basic CPU executionloop 1. Instruction Fetch 2. Instruction Decode 3. Execution (ALU) 4. Memory Access 5. Register Writeback Five Stages of RISC-V Datapath 11
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  Stage 1: InstructionFetch 5 ALU 5 5 control Reg. File PC Prog. Mem inst +4 Data Mem Fetch 32-bit instruction from memory Increment PC = PC + 4 Fetch Decode Execute Memory WB
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  Stage 2: InstructionDecode 5 ALU 5 5 control Reg. File PC Prog. Mem inst +4 Data Mem Gather data from the instruction Read opcode; determine instruction type, field lengths Read in data from register file Fetch Decode Execute Memory WB
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  Stage 3: Execution(ALU) 5 ALU 5 5 control Reg. File PC Prog. Mem inst +4 Data Mem Useful work done here (+, -, *, /), shift, logic operation, comparison (slt) Fetch Decode Execute Memory WB
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  Stage 4: MemoryAccess 5 ALU 5 5 control Reg. File PC Prog. Mem inst +4 Data Mem Used by load and store instructions only Other instructions will skip this stage R/W addr Data Data Fetch Decode Execute Memory WB
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  Stage 5: Writeback 5 ALU 55 control Reg. File PC Prog. Mem inst +4 Data Mem Write to register file • For arithmetic ops, logic, shift, etc, load. Update PC • For branches, jumps Fetch Decode Execute Memory WB
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  Hazard Handling Occurs whenan instruction depends on the results of the previous instruction which is not yet completed. 1.Data Hazards 1. Forwarding 2. Stalling( for load word ) 2.Control Hazards 1. Flushing.g ( for load word ) Flushing Data Hazard Solution
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  Stalling for load wordhazard Since the result of load instr. not available till the end of Memory Access Stage, we stall the next instructions by cycle. When result appears in Write Back Stage, we forward it to the execution stage. Load word hazard Solution
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  Control Hazards We flushthe following two instructions whenever the branch is taken. Flush decode and execute stage.
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  Features
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  RESULTS RTL SYNTHESIS OFTOP MODULE:
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  RTL SYNTHESIS OFRISC BLOCK
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  RTL SYNTHESIS OFCONTROLLER BLOCK
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  SCOPE FOR IMPROVEMENT Thecurrent RISC-V processor design can be enhanced to support more advanced operations. 1)Floating-Point Arithmetic: Add a Floating-Point Unit (FPU) to improve precision and efficiency for real number computations, supporting operations like addition, subtraction, multiplication, and division. 2)MAC Unit (Multiply-Accumulate) The MAC unit performs both multiplication and addition in a single instruction. It multiplies two numbers and adds the result to an accumulator, making it ideal for tasks involving repetitive calculations like digital signal processing (DSP) and machine learning algorithms. Efficient handling of complex arithmetic operations
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  300 275 250 225 200 175 150 125 100 75 50 25 0 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 2015 2015 2016 2016 2016 2016 2017 2017 2017 2017 2018 2018 2018 2018 2019 2019 RISC-V Foundation Growth History September 2015 to May 2019 8 May 2019 More than 250 RISC-V Members in 28 Countries Around the World 13 Universities 23 Development Tools; SW and Cloud 29 Consulting; Research 45 Semiconductor IP; IP and Design Services; Foundry Services 51 Machine Learning/AI; Commercial Chip Vendors; FPGA; Broad Market; Networking; Application Processors, Graphics 104 Individual RISC-V developers and advocates SOCIAL IMPACT
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  RISC-V is visibly disrupting the industry RISC-V foundationsummit 9 1,183 attendees at 2018 RISC-V Summit 1,836 press articles 6,314 LinkedIn Followers 8,866 @RISC_V Twitter Followers 34,200+ articles mentioning RISC-V Foundation, member companies and ISA since January 2016
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  TIME LINE (Aug.to Nov 2024) July (20th – 30th ):- Deciding the title of the project and started to read out research papers. Started to implement the Blocks using Verilog. August 1st to September 15th :- Learned about the architecture of RISC V and Completed the RTL coding for RISC V processor with necessary datapaths, Hazards and stages and testbenc for each block. September 15th to October 20th :- verify the implementation using UVM.
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  SUSTAINABLE DEVELOPMENT GOALS Low-Power Design: Optimize the RISC- V pipeline to consume minimal power by using Techniques such as clock gating, voltage scaling, and reducing dynamic power consumption in the ALU and other components.  Power-Efficient Hazards Management: Efficient forwarding and stalling mechanism can help avoid unnecessary processing and memory access  Idle Stage Reduction: Ensure pipeline stages are active only when necessary by utilizing methods like dynamic clock gating, which turns off unused pipeline stages.
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  REFERENCES 1. D. Bhandarkarand D.W. Clark, “Performance from Architecture: Comparing a RISC and a CISC with Similar Hardware Organization,”Proceedings of the 4th Int’l. Conference on ASPLOS, Santa Clara, California, April 8-11, 1991. 2. Kulshreshtha, A., Moudgil, A., Chaurasia, A. and Bhushan, B., 2021, March. Analysis of 16-Bit and 32-Bit RISC Processors. In 2021 7th International Conference on Advanced Computing and Communication Systems (ICACCS) (Vol. 1, pp. 1318-1324). IEEE. 3. Khairullah, S.S., 2022, June. Realization of a 16-bit MIPS RISC pipeline processor. In 2022 International Congress on Human- Computer. 4. M. N. Topiwala and N. Saraswathi, "Implementation of a 32-bit MIPS based RISC processor using Cadence," 2014 IEEE International Conference on Advanced Communications, Control and Computing Technologies, 2014. 5. Islam, S., Chattopadhyay, D., Das, M.K., Neelima, V. and Sarkar, R., 2006, September.Design of High-Speed-Pipelined Execution Unit of 32-bit RISC Processor. In 2006 Annual IEEE India Conference (pp. 1-5). IEEE. 6. S. P. 6. Ritpurkar, M. N. Thakare and G. D. Korde, "Design and simulation of 32-Bit RISC architecture based on MIPS using VHDL," 2015 International Conference on Advanced Computing and Communication Systems, 2015.Interaction, Optimization and Robotic Applications (HORA) (pp. 1-6). IEEE. 7. Al-sudany, S.M., Al-Araji, A.S. and Saeed, B.M., 2021. FPGA-Based Multi-Core MIPS Processor Design. IRAQI JOURNAL OF COMPUTERS, COMMUNICATION, CONTROL & SYSTEMS ENGINEERING, 21(2). 8. Wang, W., Han, J., Cheng, X. and Zeng, X., 2021. An energy-efficient cryptoextension design for RISC-V. Microelectronics Journal, 115, p.105165.