Computer architecture lecturer powerpint presentation

COMPUTER ARCHITECTURE
Chapter 2
Fetch Decode Execute Cycle

Objective
 Explain the Fetch Decode Execute Cycle:
Illustrate Data Flow in the CPU:
Identify the types of registers in the CPU
Explain the process of interrupt handling and its importance.
F e t c h - D e c o d e - E x e c u t e C y c l e

Stored Program Concept
Historically there have been 2 types of
Computers:
 Fixed Program Computers – Their
function is very specific and they
couldn’t be reprogrammed, e.g.
Calculators.
 Stored Program Computers – These
can be programmed to carry out many
different tasks, applications are stored
on them, hence the name.

 Program instructions and data
are both stored in Memory
 Instructions are fetched and
execture one after the other

Key Terms

Fetch Decode Execute Cycle:
• Fundamental process of any computer's CPU
• Three main parts: fetching the instruction, decoding it, and executing it
• Perpetual operation in the CPU
• Involves the Program Counter (PC), decoder, and Control Unit

Ba sic I nst ru c t io n C y c l e

Stages of the Fetch-Decode-Execute Cycle
 Fetch: an instruction is passed from memory to CPU
 Decode: the CPU works out the meaning of the instructions
 Execute: the CPU carries out the instruction
NB: The cycle then repeat…

Registers found in the CPU
 PC: contains the memory address of the next instruction to be fetch
 MAR: contains the address of the current instruction to be fetch
 MDR: contains the instruction/data after it is fetched from main memory
 CIR: contains the instruction/data to be decoded
 MBR: holds/stores data temporarily before using them
 ACC: stores the result of any calculation carried out in the ALU

System Buses
 Address bus: carries the address of the next item to be fetched, and it is one
directional (from CPU to main memory)
 Data bus: carries the actual data (or instruction) that has been/will be
processed. It is two direction – either way between CPU and main memory
 Control bus: carries control signals that direct the actions of the CPU. It can
be one or two directional

Simplify Schema Diagram of a Single Core CPU

Steps in the Fetch Decode Execute Cycle Content:
1. The PC holds the address of the next instruction to be fetched
2. The address in the PC is copied to the MAR via address bus
3. The PC is incremented so it contains the address of the next instruction
4. The instruction at the address held in the MAR is copied into the MDR
5. The instruction in the MDR is copied into the CIR
6. The instruction is now decoded and executed

Fetch Cycle
• CPU retrieves the instruction from memory
• Instruction stored at address specified by the PC
• PC incremented to point to the next instruction
• Steps:
• Address in PC moved to MAR
• Address placed on the address bus; control unit issues READ command
• Result appears on data bus, copied to MBR
• Program Counter incremented by one
• Content of MBR moved to CIR

Decode Cycle
• CPU interprets the instruction
• Determines what operation to perform
• Identifies opcode and operands

Execute Cycle
• CPU performs the operation specified by the instruction
• May involve:
• Reading/writing data from/to memory
• Performing arithmetic/logic operations
• Manipulating control flow of the program
• Example:
• ADD R, X (Adds content of location X to register R)
• Address portion of IR loaded into MAR
• Reference memory location read
• Contents of R and MBR added by the ALU

Additional Steps in the Instructional Cycle
• Fetch operands: Separate cycle for fetching operands before the
execute cycle
• Store results: Separate cycle for storing results after the execute cycle
• Interrupt handling: Can occur during any cycle, requires immediate
attention

Interrupt
• A signal sent from a device or from software to the processor.
This causes the processor to temporarily stop what it is doing
and service the interrupt

How to Handle Interrupt During the Fetch Execute Cycle
• At the end of the fetch execute cycle, the processor checks for interrupts. The
computer is checked for an interrupt flag.
• The processor identifies the source of interrupt and then checks for priority of
interrupt. If the interrupt priority is above the current task, the processor save the
contents of the current registers and calls the interrupt handler that services the
interrupts.
• When the service is complete the content of the registers are restored, and the
processor continues with fetch execute cycle

Instruction Cycle with Interrupt

Assignment
Describe the stages of the Fetch-
Decode-Execute Cycle (including the
use of registers and buses), in the
program execution in the table
(memory)
ADDRESS Instruction / Data
1 LOAD 5
2 ADD 6
3 STO 7
4
5 8
6 4
7
Assignment due date: 21-06-2024

Practice Question
Identify and explain the
various stages involved
in the program
execution in the diagram

Unit 1 Summary
• Review of Von Neumann Architecture
• Stored Program Concept
• Fetch-Decode-Execute-Cycle
• Registers
• Buses
• Interrupts

Trial Questions
1. What is a stored program concept?
2. Describe the stages of the Fetch Decode Execute Cycle.
3. Name and explain the purpose of at least six registers found in the CPU.
4. Name and explain the three (3) types of buses?
5. Describe the stages of the Fetch-Decode-Execute Cycle including the use of registers
and buses

Trial Questions
6. What is the primary role of the Program Counter (PC) in the Fetch Decode Execute Cycle?
7. Explain the three main stages of the Fetch Decode Execute Cycle.
8. Describe how the CPU handles an interrupt during the Fetch Decode Execute Cycle.
9. What are pipeline hazards and how do they affect the Fetch Decode Execute Cycle?
10. Illustrate with an example how indirect addressing works in the Fetch Decode Execute Cycle.
11. What is the significance of the control unit in the Decode stage of the Fetch Decode Execute Cycle?

Next :
• Introduction to assembly language programming.
• Instruction formats and addressing modes.
• Types of instruction sets: CISC and RISC.
• Relationship between ISA and hardware implementation

Computer architecture lecturer powerpint presentation

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