- 1. -Prof. Shubhangi Gaikar Assistant professor MIT ACSC,Alandi
- 2. Unit 1: Number Systems and Digital codes Introduction to Decimal, Binary and Hexadecimal number systems and their inter-conversions binary addition and binary subtraction using 2’s complement Binary Coded Decimal number Gray Codes, Gray to Binary and Binary to Gray conversion Alphanumeric representation in ASCII codes.
- 3. What is Number System ? • system for representing number of certain type. • Example: –There are several systems for representing the –counting numbers. – These include the usual base “10” or decimal system : 1,2,3 ,…..10,11,12,..99,100,… ,…..10,11,12,..99,100,…
- 4. System Base Symbols Used by humans? Used in computers? Decimal 10 0, 1, … 9 Yes No Binary 2 0, 1 No Yes Octal 8 0, 1, … 7 No No Hexa- decimal 16 0, 1, … 9, A, B, … F No No Common Number System
- 5. Decimal Binary Hexa- decimal 0 0 0 1 1 1 2 10 2 3 11 3 4 100 4 5 101 5 6 110 6 7 111 7 Counting
- 6. Decimal Number System In Decimal number system, an ordered set of ten symbols 0,1,2,3,4,5,6,7,8 and 9 are used to specify the quantities. Symbols used are known as digits. Radix or base of decimal number system is 10
- 8. Binary Number System The binary number system is a code that uses only two basic symbols i.e. 0 and 1 Generally in digital electronics 0 represents low level and 1 represents high level. Symbols in binary number system are called as bits.
- 10. Hexadecimal Number System Hexadecimal Number System has a base of sixteen. It is extensively used in Microprocessor work It uses 16 distinct symbols 0 to 9 and Ato F 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E, F
- 13. Binary to decimal conversion: (i) Get the decimal number (ii) Write the weights in exponential form (iii) Place 1 and a 0 at appropriate positions i.e. place a 1 if weight is taken during the sum and 0 otherwise. iv.) Add all the products
- 14. Hexadecimal to Decimal Conversion: In a hexadecimal number system each digit position corresponds to power of 16. The weight of the digit position in a hexadecimal number is as follows: ▪ In hexadecimal number system each digit position corresponds to appropriate power of 16. The weights of the digit positions in hexadecimal number are as follows: ………163 162 161 160 . 16-1 16-2 16-3 ▪ To convert Hexadecimal number to decimal number, multiply each hexadecimal digit by its weight and add the resulting product.
- 15. Decimal to Any Base Steps: 1. Convert integer part ( Successive Division Method ) 2. Convert fractional part ( Successive Multiplication Method )
- 16. Decimal to binary conversion Steps in Successive Division Method 1. Divide the integer part of decimal number by desired base number, store quotient (Q) and remainder (R) 2. Consider quotient as a new decimal number and repeat step1 until quotient becomes 0 3. Note down the remainders in the reverse order
- 17. Decimal Fractions to binary Multiply Rule is used Multiply bit by two and record the carry in the integer position Note down the integers in forward direction(top to bottom). (0.364) 10 = ( ?)2 0.364*2 = 0.728 0 0.728*2 = 1.456 1 0.456*2 = 0.912 0 0.912*2 =1.824 1 0.824*2= 1.648 1 Ans:(0.364) 10 = ( 0.01011)2
- 19. Hexadecimal to Binary To convert a hexadecimal number to a binary number, first write each hexadecimal digit to its 4-bit equivalent using the binary codes, and then write the binary numbers without a gap. Example : Convert (9A)16 to binary equivalent. Solution :- (9 A) (1001 1010) 2 Thus (9A)16 = (1001 1010) 2
- 20. Binary to Hexadecimal conversion (BIN to HEX) : Converting a binary to hexadecimal is a straight forward procedure. Simply break the binary number into four-bit groups starting at binary point, and replace each group with the equivalent hexadecimal symbol. Example : Convert (101101)2 to Hexadecimal equivalent 10 1101 2 D (101101)2=(2D)16
- 21. Binary Additions Binary numbers are added like decimal numbers. In decimal, when numbers sum more than 9 a carry results. In binary when numbers sum more than 1 a carry takes place. 0 + 0 = 0 1 + 0 = 1 1 + 1 = 0 + carry 1 1 + 1 + 1 = 1 + carry 1
- 22. Binary subtraction: To perform a binary subtraction you first have to represent the number to be subtracted in its negative form. This is known as its two's complement. The two's complement of a binary number is obtained by: 1. Replacing all the 1s with 0s and the 0s with 1s. This is known as its one's complement. 2. Adding 1 to this number by the rules of binary addition. Now you have the two's complement. Example: The decimal subtraction 29 - 7 = 22 is the same as adding (29) + (-7) = 22 1. Convert the number to be subtracted to its two's complement:
- 23. 2’s Complement Subtraction 00000111 (decimal 7) 11111000 (one's complement) + 00000001 (add 1) 11111001 (two's complement) 29 00011101 +-7 11111001 22 (1)00010110
- 24. Binary Coded Decimal (BCD) Code:- The binary coded decimal (BCD) code is a weighted code. This code is found very convenient for representing digits. Each group of four bits is used to represent one decimal digit. It is also called as 8421 code. This code consists of four bits which have the weights as 8 4 2 1 . The four bit combination that represents the decimal digits 0 to 9 are shown in table 1.4.
- 25. BCD Code
- 26. Non-Weighted Codes:- Non-weighted binary codes do not follow the positional weight principle. The example of non- weighted codes is gray codes, excess-3 code and alphanumeric code etc. Alphanumeric Code:- In communication along with ordinary number, we need some characters, punctuation marks and also control signals. The code we have studied so far is not enough for data communication. For overcoming this problem binary symbols are used for representing number, alphabetic character and special symbols. The binary codes which are uses to represents number, alphabetic character and special symbol are called alphanumeric code. ASCII EBCDIC
- 27. ASCII Code The ASCII code is extensively used for data communication and in computers. It is a 7-bit code, so it can represents 27 or 128 different characters. It can represent decimal number 0-9, letters of alphabets in lower case and upper case, special symbol and control instructions. Each symbol has 7- bit code which is made up of a 3-bit group followed by a 4-bit group. The number is represented by 8421 code.
- 29. Gray Code: Binary to Gray Converter: In this conversion the most significant bit (MSB) is copied as it is, so these represents MSB of gray code, then going from left to right add each adjacent pair of binary digits to get the next gray code. After the addition forget the about carry.
- 30. Gray Code
- 31. Gray To Binary Code conversion In this conversion first write MSB bit as it is of a gray code, this one is an MSB bit of binary code, and then add each MSB of binary code to the next bit of gray code. If carry is generated then neglect the carry.
- 32. • Boolean algebra: Boolean algebra is mathematics of digital system. Boolean algebra is aconvenient and systematic way of expressing and analyzing the operation of logic circuit. ➢ Rules and Law’s of Boolean Algebra: • Law of Intersection: 1) A.1 = A 2) A.0 = 0 • Law of Union: 3) A+1 = 1 4) A+0 = A • Law of Tautology : 5) A.A = A 6) A+A = A • Law of Complements: 7) A.Ā = 0 8) A+ Ā = 1 • Law of Double-Negation: 9) Ā = A • Law of Commutation: 10) A.B =B.A 11) A+B = B+A • Law of Association: 12) (A+B)+C = A+(B+C) 13) (A.B).C = A.(B.C) • Law of Distribution: 14) A.(B+C) = AB + AC 15) A+(B.C) = (A+B).(A+C)
- 33. • Law of Absorption: 16) A+A.B = A 17) A.(A+B) = A 18) A.B+B = A+B 19) A.(Ā + B) = A.B 20) A.B+B = A+B = B Input Intermediate Value L.H Output .S R. H.S A B A.B A B A.B A + B 0 0 0 1 1 1 1 0 1 0 0 0 1 1 1 0 0 0 0 1 1 1 1 1 0 0 0 0 • Demorgans Theorems: A) Demorgans 1st Theorem: The first theorem states that, the complement of product is equal to the sum of the complements. The complement of two or more variable ANDed is the same as the OR of the complement of each individual variable. L.H.S R.H.S A.B = A + B A A B y = A.B Truth Table of Demorgans 1st Thm A + B
- 34. A == B Input Intermediate Value L.H Output .S R. H.S A B A+B A B A+B A . B 0 0 0 1 1 1 1 0 1 1 1 0 0 0 1 0 1 0 1 0 0 1 1 1 0 0 0 0 A B Y=A+B Y A . B Truth Table of Demorgans 2nd Thm B) Demorgans 2nd Theorem : The demorganssecond theorem states that, the complement of sum is equal to the product of the complements. A + B = A . B L.H.S R.H.S
- 35. Logic gate
- 36. BinaryAdder The most basic arithmetic operation is addition. The circuit, which performs the addition of two binary numbers is known as Binary adder. First, let us implement an adder, which performs the addition of two bits. HalfAdder Half adder is a combinational circuit, which performs the addition of two binary numbers A and B are of single bit. It produces two outputs sum, S & carry, C. The Truth table of Half adder is shown below. Inputs Outputs A B C S 0 0 0 0 0 1 0 1 1 0 0 1 1 1 1 0 When we do the addition of two bits, the resultant sum can have the values ranging from 0 to 2 in decimal. We can represent the decimal digits 0 and 1 with single bit in binary. But, we can’t represent decimal digit 2 with single bit in binary. So, we require two bits for representing it in binary. Let, sum, S is the Least significant bit and carry, C is the Most significant bit of the resultant sum. For first three combinations of inputs, carry, C is zero and the value of S will be either zero or one based on the number of ones present at the inputs. But, for last combination of Figure Half Adder 36
- 37. 37 inputs, carry, C is one and sum, S is zero, since the resultant sum is two. The circuit diagram of Half adder is shown in the following figure. In the above circuit, a two input Ex-OR gate & two input AND gate produces sum, S & carry, C respectively. Therefore, Half-adder performs the addition of two bits. Full Adder using Two Half Adders:- Full adder is a combinational circuit, which performs the addition of three bits A, B and Cin. Where, A & B are the two parallel significant bits and Cin is the carry bit, which is generated from previous stage. This Full adder also produces two outputs sum, S & carry, Cout, which are similar to Half adder. The Truth table of Full adder is shown below. Inputs Outputs A B Cin Cout S 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 When we do the addition of three bits, the resultant sum can have the values ranging from 0 to 3 in decimal. We can represent the decimal digits 0 and 1 with single bit in binary. But, we can’t represent the decimal digits 2 and 3 with single bit in binary. So, we require two bits for representing those two decimal digits in binary. Let, sum, S is the Least significant bit and carry, Cout is the Most significant bit of resultant sum. It is easy to fill the values of outputs for all combinations of inputs in the truth table. Just count the number of ones present at the inputs and write the equivalent binary number at outputs. If Cin is equal to zero, then Full adder truth table is same as that of Half adder truth table. The sum, S is equal to one, when odd number of ones present at the inputs. We know that Ex-OR gate produces an output, which is an odd function. So, we can use either two 2input Ex-OR gates or one 3-input Ex-OR gate in order to produce sum, S. We can implement carry, Cout using two 2-input AND gates & one OR gate. The circuit diagram of Full adder is shown in the following figure.
- 38. This adder is called as Full adder because for implementing one Full adder, we require two Half adders and one OR gate. If Cin is zero, then Full adder becomes Half adder. We can verify it easily from the above circuit diagram or from the Boolean functions of outputs of Full adder. • 4-bit Binary Adder: The 4-bit binary adder performs the addition of two 4-bit numbers. Let the 4-bit binary numbers, A=A3A2A1A0 and B=B3B2B1B0. We can implement 4-bit binary adder in one of the two following ways. • Use one Half adder for doing the addition of two Least significant bits and three Full adders for doing the addition of three higher significant bits. •Use four Full adders for uniformity. Since, initial carry Cin is zero, the Full adder which is used for adding the least significant bits becomes Half adder. Figure: Full adder 38
- 39. For the time being, we considered second approach. The block diagram of 4-bit binary adder is shown in the following figure. Here, the 4 Full adders are cascaded. Each Full adder is getting the respective bits of two parallel inputs A & B. The carry output of one Full adder will be the carry input of subsequent higher order Full adder. This 4-bit binary adder produces the resultant sum having at most 5 bits. So, carry out of last stage Full adder will be the MSB. In this way, we can implement any higher order binary adder just by cascading the required number of Full adders. This binary adder is also called as ripple carry (binary) adder because the carry propagates (ripples) from one stage to the next stage. 4-bit Binary Subtractor The 4-bit binary subtractor produces the subtraction of two 4-bit numbers. Let the 4bit binary numbers, A=A3A2A1A0 and B=B3B2B1B0. Internally, the operation of 4-bit Binary subtractor is similar to that of 4-bit Binary adder. If the normal bits of binary number A, complemented bits of binary number B and initial carry (borrow), Cin as one are applied to 4-bit Binary adder, and then it becomes 4-bit Binary subtractor. The block diagram of 4-bit binary subtractor is shown in the following figure. Figure 4-bit binary adder 39
- 40. This 4-bit binary subtractor produces an output, which is having at most 5 bits. If Binary number A is greater than Binary number B, then MSB of the output is zero and the remaining bits hold the magnitude of A-B. If Binary number A is less than Binary number B, then MSB of the output is one. So, take the 2’s complement of output in order to get the magnitude of A-B. In this way, we can implement any higher order binary subtractor just by cascading the required number of Full adders with necessary modifications. Universal Adder / Subtractor: The circuit, which can be used to perform either addition or subtraction of two binary numbers at any time, is known as Universal Adder / subtractor. Both, Binary adder and Binary subtractor contain a set of Full adders, which are cascaded. The input bits of binary number A are directly applied in both Binary adder and Binary subtractor. There are two differences in the inputs of Full adders that are present in Binary adder and Binary subtractor. • The input bits of binary number B are directly applied to Full adders in Binary adder, whereas the complemented bits of binary number B are applied to Full adders in Binary subtractor. • The initial carry, C0 = 0 is applied in 4-bit Binary adder, whereas the initial carry (borrow), C0 = 1 is applied in 4-bit Binary subtractor. Figure: 4-bit Binary Subtractor 40
- 41. We know that a 2-input Ex-OR gate produces an output, which is same as that of first input when other input is zero. Similarly, it produces an output, which is complement of first input when other input is one. Therefore, we can apply the input bits of binary number B, to 2-input Ex-OR gates. The other input to all these Ex- OR gates is C0. So, based on the value of C0, the Ex-OR gates produce either the normal or complemented bits of binary number B. The 4-bit binary adder / subtractor produces either the addition or the subtraction of two 4-bit numbers based on the value of initial carry or borrow, C0. Let the 4-bit binary numbers, A=A3A2A1A0 and B=B3B2B1B0. The operation of 4-bit Binary adder / subtractor is similar to that of 4-bit Binary adder and 4-bit Binary subtractor. Apply the normal bits of binary numbers A and B & initial carry or borrow, C0 from externally to a 4-bit binary adder. If initial carry, C0 is zero, then each full adder gets the normal bits of binary numbers A & B. So, the 4-bit binary adder / subtractor produces an output, which is the addition of two binary numbers A & B. If initial borrow, 𝐶0 is one, then each full adder gets the normal bits of binary number A & complemented bits of binary number B. So, the 4-bit binary adder / subtractor produces an output, which is the subtraction of two binary numbers A & B. Therefore, with the help of additional Ex-OR gates, the same circuit can be used for both addition and subtraction of two binary numbers. Figure 4-bit adder/subtractor 41
- 43. Figure Block Diagram of an ALU 43 Introduction to ALU: An arithmetic logic unit (ALU) is a combinational digital electronic circuit that performs arithmetic and bitwise operations on integer binary numbers. This is in contrast to a floating-point unit (FPU), which operates on floating point numbers. An ALU is a fundamental building block of many types of computing circuits, including the central processing unit (CPU) of computers, FPUs, and graphics processing units (GPUs). A single CPU, FPU or GPU may contain multiple ALUs. The inputs to an ALU are the data to be operated on, called operands, and a code indicating the operation to be performed and, optionally, status information from a previous operation; the ALU's output is the result of the performed operation. In many designs, the ALU also exchanges additional information with a status register, which relates to the result of the current or previous operations.
- 44. The logic circuits are broadly classified as combinational circuit and sequential circuits. In combinational circuits the response of the circuit is decided by a set of inputs existing at that instant of time. By changing the inputs, the output of a combinational circuit can be change. ❖ Multiplexers:- (Many to one): The multiplexer means “many into one”. The circuit which is accepts inputs from “n” devices, select any one signal by control lines and allows that signal to appear at the output. It has “n” input lines. “m” control lines and only one output. To make multiplexers, combination of logic gates are used like AND, OR, NAND etc. The relation between number of input signals and control lines is n = 2m . In addition all these lines a MUX have master control line called the strobe. When strobe=1 then MUX will enable and Strobe = 0 then MUX will disable. Multiplexer (MUX) N:1 “n” of inputs Single Output ‘m’ control Lines
- 45. • 2 To 1 Multiplexer: D0 D1 Y-O/P Select I/P “S” Figure (a): 2 To 1 Multiplexer (b)Truth Table of 2:1 MUX S D1 D0 O/P=Y 0 0 0 0 0 0 1 D0 1 1 0 D1 1 1 1 D1 The figure a) shows the 2 to 1 MUX and figure b) shows the truth table of 2 to 1 MUX. According to the relation n = 2m , to design 2 to 1 MUX the 1 control line is required. The D0 and D1 are the data inputs and S is the control line is used. When S= 0, then first AND gate receives the bothd its inputs as (1,1), therefore, data D0 is directed at the output. When S=1, then second AND receives both its input as (1,1), therefore, data D1 is directed to the output. • 4 To 1 Multiplexer: B A A B Y I/P-2 I/P-3 I I/P-1 II III IV I/P-4 Figure a) Logic Diagram of 4:1 Multiplexer
- 46. A 4 To 1 MUX has 4 inputs, 2- control lines and single output . According to the relation n =2m the 2 –control lines are used. The each AND gate has 3- inputs, two inputs from the control lines and one data input. Case I:- When A=0, B=0 The I-AND gate receives complement of A and complement of B control lines i.e (1,1), and 1- data input is preset. Therefore AND gate I receives (1,1,1) at its input side, the output of I-AND gate is high(1). The AND gates II, III and IV receives one of its input is ‘0’, therefore, all three AND gate output is low(0). The OR-gate receieves one input as high(1) and all other inputs of OR gate are low(0). So, Data input i.e I/P-1 is appeared at the output Y. Case II:- When A=0, B=1 The II-AND gate receives complement of A and B control lines i.e (1,1), and 1-data input is present. Therefore AND gate II receives (1,1,1) at its input side, the output of II-AND gate is high(1). The AND gates I, III and IV receives one of its input is ‘0’, therefore, all three AND gate output is low(0). The OR-gate receives one input as high(1) and all other inputs of OR gate are low(0). So, Data input i.e I/P-2 is appeared at the output Y. Similarly, in other cases such as A=1 and B=0, A=1 and B=1, the I/P-3 and I/p-4 will appeared at the output respectively. Truth Table of 4:1 Multiplexer A B Y- output 0 0 I/P-1 0 1 I/P-2 1 0 I/P-3 1 1 I/P-4
- 47. . • Advantages of Multiplexers:- 1)It reduces the number of wires required to pass data from source to destination. 2)Ir does not require the simplification of logic expressions. 3)It minimizes the component count in IC packages by avoiding the repetition of the same signal processing circuits and logic blocks for every channel. 4)It also minimizes the number of IC’s required to be used. 5)It reduces the cost of circuits. 6)It simplify the logic design. • Application of Multiplexers:- 1)It can be used as data selector to select one output of many data inputs. 2)It can be used for data sorting. 3)It is used in designing the combinational circuit. 4)It can be used for parallel to serial data conversion. 5)It can be used as waveform generater.
- 48. . ❖ Demultiplexer: The above figure shows the 1:2 demultiplexer. Designing of 1:2 demultiplexer one control line, one data input which is common to both the AND gates and two output lines are required. The number of control lines required to design the demultiplexer is calculated by using the relation n = 2m . S O/P 0 Y0=Data i/p 1 Y1=Data i/p “n” O/P Lines 1: n Demultiplexer Single I/P “m” Control The demultiplexer is a logic circuit which allows a common input to be directed to any one of the “n” available output depending on the control lines. It has one input line , “m” control lines and “n” output lines. The number of control lines “m” must satisfy the relation n = 2m . So the demultiplexer is also called as one to many. • 1: 2 To Demultiplexer: Y0 Y0 Data I/P “S” Control Line
- 49. When control line S = 0, then first AND receives both of its input high(1,1). The second AND gate receives one of its input is low(0), therefore the output of the second AND gate is low and the data input is directed to the output line Y0. When control line S = 1, then second AND receives both of its input high(1,1). The first AND gate receives one of its input is low(0), therefore the output of the first AND gate is low and the data input is directed to the output line Y1. • 1:4 Demultiplexer: The above figure shows an 1:4 demultiplexer and its truth table. It has only one input and four output, depending on control line the input will come at different output lines. According to the relation n =2m , for 1: 4 demux two control lines are required by such as A and B. It is constructed by using four AND gate and 2 NOT gates. A B O/P 0 0 Y1 0 1 Y2 1 0 Y3 1 1 Y4 A B A B I II IV Data I/P Y1 Y2 Y3 III Y4 Figure Diagram a) 1:4 Demultiplexer Logic
- 50. • Applications of Demultiplxer:- 1) Demux are used as data routers. 2) It can be used as address decoder. 3) It can be used as function generator just like multiplexer. • Comparison of Multiplexerand Demultiplexer:- Sr. No. Multiplexer Demultiplexer 1 It is a combinational logic circuit It is also a combinational logic circuit 2 Multiplexer means many into one demultiplexer means one to many 3 It has “n” number of data inputs and single output. It has single data input and “n” output. 4 It has “m” number of control lines It has “m” number of control lines 5 It accepts many input and gives out a single output depending on the status of control lines. It accepts a single input and distributes it over several outputs depending of the ststus of the select lines 6 Multiplexer is used as data selector. Demultiplexer used as data distributer and router.
- 51. ❖Encoders:- The decimal code most widely used code in our day to day life. But decimal is not accepted by digital system and hence it is necessary to convert a decimal code into a suitable binary code so that digital system can understand. The “Encoder” is a circuit which converts the data which is in general into desired code i. e binary. The following circuits are the examples of encoders which converts one specific code to binary. 1) Decimal to Binary 2) Hexadecimal to binary 3) Octal to binary. ❖ Decimal to Binary Encoder or code Converter: Encoder Or Code Converter Binary Or BCD O/P Decimal or Hexadeci mal A C B D Figure a). Block Diagram of Encoder or code converter Vcc 1 2 3 4 5 6 7 8 9 Figure.b) Logic Diagram Decimal of to BCD Encoder
- 52. Figure c) Truth table for Decimal to Binary encoder Decimal Digit D C B A 0 0 0 0 0 1 0 0 0 1 2 0 0 1 0 3 0 0 1 1 4 0 1 0 0 5 0 1 0 1 6 0 1 1 0 7 0 1 1 1 8 1 0 0 0 9 1 0 0 1 The above figure a) the block diagram of decimal to BCD encoder and figure c) shows the BCD output for each decimal. When any switch corresponding to decimal digit is pressed the corresponding line becomes high. If switch “5” is pressed, the input line “5” becomes high, so “1” input will appear across the OR gates A and C.and “0” output on B and D gates, which is BCD code for decimal “5”. Similarly when switch “9” is pressed the code generated will be 1001 and so on.
- 53. ❖Priority Encoder: The priority encoder includes necessary logic circuit, which is needed to ensure that when two or more inputs are activated at the same time, only the code which corresponds to highest number input is generated at the output. For example, If ‘5’ and ‘7’ inputs are made high simultaneously, the circuit which generate a code of ‘7’ at the output. ❖ IC-74148 Priority Encoder : The IC-74148 accepts data from 8- active low inputs and generates inverted binary data on the active low outputs. Apart from supply and ground line, there are two enables lines such as E1 and E0. These are the active low enable input lines. The line GS is called group signal. The GS becomes low when an input is activated. The E1 and E0 lines decide the priority of the input signals. The priority encoder IC- 74148 is assuming a priority for encoder’s inputs, so that when two or more inputs are active, only the input which is highest priority is encoded. IC-74148 Priority Encoder Active Low Inputs VCC GND E1 E0 GS A B C
- 54. ❖Decoders: Decoding is a process in which the information presents in one code obtained back into desired code. For example, the binary output of digital circuit is converted into decimal system by using decoders. Thus, decoders are opposite of encoder. A decoder is similar to the “Demultiplexer” except that there is no data input. The only inputs are the control signals. ❖ 2 To 4 Decoder: Strobe Signal A B O/P Selected 1 0 0 O1 1 0 1 O2 1 1 0 O3 1 1 1 O4 The number of output lines are 4 , therefore, number of address lines “n” is given by, 4 = 2n , n=2. A B A B I II IV Strobe Signal O1 O2 O3 III O4 Figure a) 2 To 4 Decoder Logic Diagram
- 55. The above figure a) shows the 2 to 4 decoder. The decoder doesn’t habe an data input, only control lines are used. Therefore, 2-control lines A and B are used. The output lines are activated according the status of the control lines. If Control lines are A= 0 and B=0 then NAND gate I will receives both its input high. Therefore, its outputs goes to low. Hence output line O1 becomes low and so on. ❖ Decoder IC -74138(BCD to Octal): E1 E2 E3 C B A Output 1 0 0 0 0 0 O1 1 0 0 0 0 1 O2 1 0 0 0 1 0 O3 1 0 0 0 1 1 O4 1 0 0 1 0 0 O5 1 0 0 1 0 1 O6 1 0 0 1 1 0 O7 1 0 0 1 1 1 O8 This is called a 3:8 decoder or binary to octal converter. It is a TTL IC works on +5Volt power supply. It has 3 control lines A,B and C can also be called as address lines. It has 8-output Address Inputs IC-74138 Decoder VCC GND E1 E2 E3 O1 O2 O3 O4 Output Lines O5 O6 O7 O8
- 56. Reference Books: 1. Digital Fundamentals: Floyd T.M., Jain R.P., Pearson Education 2. Digital Electronics: Jain R.P., Tata McGraw Hill 3. Digital Principles and Applications: Malvino Leach, Tata McGraw-Hill 4. M.Morris Mano, “ Digital Design “ 3rdEdition, PHI, NewDelhi.