The document outlines the basic operational concepts of a CPU, including the roles of registers like the MAR, MDR, and instruction register in executing tasks. It describes the functioning of buses in computer architecture, detailing their operation, types, and arbitration methods for managing access to shared communication links among subsystems. The bus structure is essential for connecting input/output devices to the CPU and memory, facilitating data transfer through control, address, and data lines.

1. Basic Operational Concepts
• To Execute a given task as per the
appropriate program
• Program consists of list of instructions
stored in memory
1

2. Interconnection between Processor and Memory 2

3. Registers
Registers are fast stand-alone storage locations that hold data
temporarily. Multiple registers are needed to facilitate the
operation of the CPU.
Some of these registers are
 Two registers-MAR (Memory Address Register) and
MDR (Memory Data Register) : To handle the data
transfer between main memory and processor. MAR-
Holds addresses, MDR-Holds data
 Instruction register (IR) : Hold the Instructions that is
currently being executed
 Program counter: Points to the next instructions that is
to be fetched from memory
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4. Examples: - ADD LOCA, R0
• This instruction adds the operand at memory
location LOCA, to operand in register R0 & places
the sum into register.
• This instruction requires the performance of
several steps,
1. First the instruction is fetched from the memory into
the processor.
2. The operand at LOCA is fetched and added to the
contents of R0
3. Finally the resulting sum is stored in the register R0

5. Operating steps
1. Programs reside in the memory & usually get these
through the I/P unit.
2. Execution of the program starts when the PC is set to point
at the first instruction of the program.
3. Contents of PC are transferred to MAR and a Read Control
Signal is sent to the memory.
4. After the time required to access the memory elapses, the
address word is read out of the memory and loaded into
the MDR.
5. Now contents of MDR are transferred to the IR & now the
instruction is ready to be decoded and executed.
6. If the instruction involves an operation by the ALU, it is
necessary to obtain the required operands.

6. Operating steps
7. An operand in the memory is fetched by sending its
address to MAR & Initiating a read cycle.
8. When the operand has been read from the memory
to the MDR, it is transferred from MDR to the ALU.
9. After one or two such repeated cycles, the ALU
can perform the desired operation.
10. If the result of this operation is to be stored in the
memory, the result is sent to MDR.
11. Address of location where the result is stored is
sent to MAR & a write cycle is initiated.
12. The contents of PC are incremented so that PC
points to the next instruction that is to be executed.

7. Bus Structures and Bus
Operation
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8. Buses
• A bus is a shared communication link, which uses
one set of wires to connect multiple subsystems.
• The two major advantages of the bus
organization are versatility and low cost.
• Most modern computers use single bus
arrangement for connecting I/O devices to CPU &
Memory.
• The bus enables all the devices connected to it to
exchange information.
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9. Buses
• Bus consists of 3 set of lines : Address, Data,
Control
• Processor places a particular address (unique for
an I/O Dev.) on address lines.
• Device which recognizes this address responds to
the commands issued on the Control lines.
• Processor requests for either Read / Write.
• The data will be placed on Data lines.

10. Data Bus
• Carries data
– Remember that there is no difference between
“data” and “instruction” at this level
• Width is a key determinant of performance
– 8, 16, 32, 64 bit
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11. Address bus
• Identify the source or destination of data
• e.g. CPU needs to read an instruction (data)
from a given location in memory
• Bus width determines maximum memory
capacity of system
– e.g. 8080 has 16 bit address bus giving 64k
address space
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12. Control Bus
• Control and timing information
– Memory read/write signal
– Interrupt request
– Clock signals
– Reset
– Bus request / bus grant
– Transfer ACK
– I/O read and I/O write
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13. Bus Interconnection Scheme
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14. Big and Yellow?
• What do buses look like?
– Parallel lines on circuit boards
– Ribbon cables
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15. Bus Types
• Bus is a shared communication link.
• It is used to connect multiple subsystems.
Single bus structure
Multiple bus structure
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16. Single bus structure
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17. Multiple bus structure - Traditional (ISA)
(with cache)
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18. High Performance Bus
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19. Bus Operations
• Bus includes:
1. Address lines
2. Data lines
3. Control lines
• Data transfer can be in two ways:
1. Synchronous bus
2. Asynchronous bus
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20. Bus Operations
1. Synchronous bus - All devices derive timing
information from a common clock cycle.
2. Asynchronous bus – common clock cycle is
eliminated and data transfer is achieved by
handshake between processor and device
being connected
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21. Bus Operations
Handshake
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22. BUS Arbitration
• Bus Arbitration refers to the process by which the current bus master
accesses and then leaves the control of the bus and passes it to the
another bus requesting processor unit.
• The controller that has access to a bus at an instance is known as Bus
master.
• A conflict may arise if the number of DMA controllers or other
controllers or processors try to access the common bus at the same
time, but access can be given to only one of those.
• Only one processor or controller can be Bus master at the same point
of time.
• To resolve these conflicts, Bus Arbitration procedure is implemented
to coordinate the activities of all devices requesting memory
transfers.
• The selection of the bus master must take into account the needs of
various devices by establishing a priority system for gaining access to
the bus.
• The Bus Arbiter decides who would become current bus master.

23. BUS Arbitration
• There are two approaches to bus arbitration:
–Centralized bus arbitration – A single bus
arbiter performs the required arbitration.
–Distributed bus arbitration – All devices
participate in the selection of the next bus
master.
• Methods of BUS Arbitration –
There are three bus arbitration methods:
• Daisy Chaining method
• Polling or Rotating Priority method
• Fixed priority or Independent Request method

24. Daisy Chaining method
• It is a centralized bus arbitration method. During
any bus cycle, the bus master may be any device –
the processor or any DMA controller unit,
connected to the bus.

25. Polling or Rotating Priority
method
• In this method, the devices are assigned unique
priorities and complete to access the bus, but the
priorities are dynamically changed to give every
device an opportunity to access the bus.

26. Fixed priority or Independent Request
method
• In this method, the bus control passes from one
device to another only through the centralized
bus arbiter.