GANDHI INSTITUTE FOR EDUCATION & TECHNOLOGY
FIFT SEMESTER EXAMINATION-2009
COMPUTER ARCHITECTURE & ORGANIZATION
FULL MARK:...
GANDHI INSTITUTE FOR EDUCATION & TECHNOLOGY
FIFT SEMESTER EXAMINATION-2009
COMPUTER ARCHITECTURE & ORGANIZATION
FULL MARK:...
GANDHI INSTITUTE FOR EDUCATION & TECHNOLOGY
FIFT SEMESTER EXAMINATION-2009
COMPUTER ARCHITECTURE & ORGANIZATION
FULL MARK:...
GANDHI INSTITUTE FOR EDUCATION & TECHNOLOGY
FIFT SEMESTER EXAMINATION-2009
COMPUTER ARCHITECTURE & ORGANIZATION
FULL MARK:...
GANDHI INSTITUTE FOR EDUCATION & TECHNOLOGY
FIFT SEMESTER EXAMINATION-2009
COMPUTER ARCHITECTURE & ORGANIZATION
FULL MARK:...
GANDHI INSTITUTE FOR EDUCATION & TECHNOLOGY
FIFT SEMESTER EXAMINATION-2009
COMPUTER ARCHITECTURE & ORGANIZATION
FULL MARK:...
GANDHI INSTITUTE FOR EDUCATION & TECHNOLOGY
FIFT SEMESTER EXAMINATION-2009
COMPUTER ARCHITECTURE & ORGANIZATION
FULL MARK:...
GANDHI INSTITUTE FOR EDUCATION & TECHNOLOGY
FIFT SEMESTER EXAMINATION-2009
COMPUTER ARCHITECTURE & ORGANIZATION
FULL MARK:...
GANDHI INSTITUTE FOR EDUCATION & TECHNOLOGY
FIFT SEMESTER EXAMINATION-2009
COMPUTER ARCHITECTURE & ORGANIZATION
FULL MARK:...
GANDHI INSTITUTE FOR EDUCATION & TECHNOLOGY
FIFT SEMESTER EXAMINATION-2009
COMPUTER ARCHITECTURE & ORGANIZATION
FULL MARK:...
GANDHI INSTITUTE FOR EDUCATION & TECHNOLOGY
FIFT SEMESTER EXAMINATION-2009
COMPUTER ARCHITECTURE & ORGANIZATION
FULL MARK:...
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Co question 2009

  1. 1. GANDHI INSTITUTE FOR EDUCATION & TECHNOLOGY FIFT SEMESTER EXAMINATION-2009 COMPUTER ARCHITECTURE & ORGANIZATION FULL MARK: 70 TIME: - 3HOURS Prepared by Asst.Prof S.K.Rath (CSE DEPARTMENT) Page 1 Answer Question No.1 which is compulsory and any five from the rest. The figure in the right hand margin indicates marks. 1. Answer the following question: 2*10=20 (a)Increasing the number of addressing mode improve the flexibility in writing assembly language program, but reduce the performance? Ans: Increase the number of addressing mode improve the flexibility in writing assembly language programming since it reduce the instruction length by having short field for address .it provides powerful aid to the programmer for complex data handling. (b) How ISR different from subroutine. Ans: Subroutine is a portion of code within a larger program, which performs a specific task and is relatively independent of the remaining code. Interrupt Service Routines (ISRs) are to handle hardware interrupts. These routines are not independent threads, but more like signals. ISR is called if any thread is suspended by an interrupt (c)Is IR same as IP Register? Justify your answer. Ans: IR is not same as IP. IR stands for instruction register which holds the instruction that is currently being executed. IP strands for instruction pointer which is used to store the memory location of the next instruction to be executed. (d) What do you mean by memory mapping? How many 128*8 RAM chip are needed to provide a memory capacity of 2048 byte. Ans: Memory mapping is the techniques for managing the peripheral device, used on much microprocessor system and on some smaller microprocessor system. The control register of the peripheral device appear to the processor as word in memory whose content can be written and read using fetch operation. Desired memory capacity=2048 byte=2048*8 bits Number of chip required =2048*8/128*8=16
  2. 2. GANDHI INSTITUTE FOR EDUCATION & TECHNOLOGY FIFT SEMESTER EXAMINATION-2009 COMPUTER ARCHITECTURE & ORGANIZATION FULL MARK: 70 TIME: - 3HOURS Prepared by Asst.Prof S.K.Rath (CSE DEPARTMENT) Page 2 (e) What will be the 2’s complement of the given number which is in signed binary representation? 00010010 01001010 1’s complement= 11101101 10110101 2’s complement= 11101101 10110110 (f)signed 2’s complement representation is preferred over signed 1’s complement representation, why? Ans: 2’s complement is preferred over 1’s complement representation because 2’s complement is having one encoding for zero. (g) What is the basic function of RESET signal in 8085 microprocessor? Ans: RESET signal in 8085 microprocessor perform 1) Sets the program counter to zero. 2) Resets the interrupt enable and HLDA flip-flops. 3) Tristates the data bus,address bus nd control bus. 4) Affetcs the contents of processor's internal registers randomly. 5) Reset Out:This active high signal indicates that processor is being reset.This signal is synchronized to processor clock nd ir can be used to reset other devices connected in the system (h) What do you mean by instruction format? Ans: an instruction format provides the following instruction to the CPU. 1) Operation to be performed by the instruction. 2) Operand on which operation has to be performed. 3) Address of the operand 4) Address of next instruction to be fetched. (i) Difference between page fault and cache miss. Ans: page fault is said to occur if the page requested by the processor is not in the main memory. The requested page must bought from the disk into the main memory before the access can proceed. Cache miss is said to be occurred if the block requested by the processor is not in the cache memory.
  3. 3. GANDHI INSTITUTE FOR EDUCATION & TECHNOLOGY FIFT SEMESTER EXAMINATION-2009 COMPUTER ARCHITECTURE & ORGANIZATION FULL MARK: 70 TIME: - 3HOURS Prepared by Asst.Prof S.K.Rath (CSE DEPARTMENT) Page 3 (j) What do you mean by Von Neumann Architecture? Ans: According to Von Neumann architecture it is based on stored program concept. In which all the instruction and data are stored in memory. The architecture mainly consists of basic function al unit. 1) Input unit 2) CPU 3) Memory unit 4) Output unit. 2) A) what do you mean by instruction cycle? Explain step by step the instruction execution process. Ans: The time period during which one instruction is fetched from memory and executed when a computer is given an instruction in machine language. There are typically four stages of an instruction cycle that the CPU carries out: 1. Fetch the instruction from memory. This step brings the instruction into the instruction register, a circuit that holds the instruction so that it can be decoded and executed. 2. Decode the instruction. 3. Read the effective address from memory if the instruction has an indirect address. 4. Execute the instruction. Steps 1 and 2 are called the fetch cycle and are the same for each instruction. Steps 3 and 4 are called the execute cycle and will change with each instruction. The term refers to both the series of four steps and also the amount of time that it takes to carry out the four steps.An instruction cycle also is called machine cycle. B) An instruction is stored at location 300 with an address field at location 301. The address field has the value 400. A process register R1 contain the number 200. Calculate the effective address, if the addressing mode of instruction is i) direct ii) immediate iii) relative iv) index with R1 register. Ans: given that Processor Register (R1)=200 1) Direct=400 2) Immediate= 301
  4. 4. GANDHI INSTITUTE FOR EDUCATION & TECHNOLOGY FIFT SEMESTER EXAMINATION-2009 COMPUTER ARCHITECTURE & ORGANIZATION FULL MARK: 70 TIME: - 3HOURS Prepared by Asst.Prof S.K.Rath (CSE DEPARTMENT) Page 4 3) Relative= 302+400=702 4) Indexed with R1 as the index register= 200+400=600 3) A) Distinguished between hardwired control unit and micrprogrammed control unit. Ans: A hardwired control unit has a processor that generates signals or instructions to be implemented in correct sequence. This was the older method of control that works through the use of distinct components, drums, a sequential circuit design, or flip chips. It is implemented using logic gates & flip flops. It is faster, less flexible & limited in complexity A micro programmed control unit on the other hand makes use of a micro sequencer from which instruction bits are decoded to be implemented. It acts as the device supervisor that controls the rest of the subsystems including arithmetic and logic units, registers, instruction registers, off-chip input/output, and buses. It is slower, more flexible & greater complexity B) Difference between Static RAM and pseudo Static RAM. Ans: Pseudo Static RAM is one of the variations of DRAM. The only difference between Pseudo Static RAM and DRAM is that earlier has memory refresh controller built in. Thus, since the RAM user need not worry about refreshing, the device appears to behave much like an SRAM. However, in contrast to true SRAM, a PSRAM may be busy refreshing itself when accessed, which could slow access time and add some system complexity. Nevertheless, PSRAM is a popular low cost high density memory alternative to SRAM in many embedded systems. Or SRAM (Static RAM) Data is stored in cross-coupled inverters Large cell - requires several transistors (6T cell standard) Fast access time / Low density Integrates easily into logic fab processes DRAM (Dynamic RAM) Data is stored in form of charged capacitors Small cell - requires one capacitor and one transistor “Refresh” operation required every few milliseconds Slower access time but much higher density than SRAM
  5. 5. GANDHI INSTITUTE FOR EDUCATION & TECHNOLOGY FIFT SEMESTER EXAMINATION-2009 COMPUTER ARCHITECTURE & ORGANIZATION FULL MARK: 70 TIME: - 3HOURS Prepared by Asst.Prof S.K.Rath (CSE DEPARTMENT) Page 5 4) A) Explain Virtual memory techniques briefly. Ans: if your computer lacks the random access memory (RAM) needed to run a program or operation, Windows uses virtual memory to compensate. Virtual memory combines your computer’s RAM with temporary space on your hard disk. When RAM runs low, virtual memory moves data from RAM to a space called a paging file. Moving data to and from the paging file frees up RAM to complete its work. The purpose of virtual memory is to enlarge the address space, the set of addresses a program can utilize. For example, virtual memory might contain twice as many addresses as main memory. A program using all of virtual memory, therefore, would not be able to fit in main memory all at once. Nevertheless, the computer could execute such a program by copying into main memory those portions of the program needed at any given point during execution. Virtual Memory Advantages --------------------------------- You can run more applications at once. You can run larger applications with less real RAM. Applications may launch faster because of File Mapping. You don't have to buy more memory (RAM). Virtual Memory Disadvantages --------------------------------- Applications run slower. It takes more time to switch between applications. Less hard drive space for your use. Reduced system stability B) What is multicomputer? Is it different from multiprocessor system? Justify. Ans: Multicomputer-- A computer made up of several computers. The term generally refers to an architecture in which each processor has its own memory rather than multiple processors with a shared memory. Something similar to parallel computing. Distributed computing deals with hardware and software systems containing more than one processing element or storage element, concurrent processes, or multiple programs, running under a loosely or tightly controlled regime. Multiprocessor-- A multiprocessor system is simply a computer that has more than one CPU on its motherboard. If the operating system is built to take advantage of this,
  6. 6. GANDHI INSTITUTE FOR EDUCATION & TECHNOLOGY FIFT SEMESTER EXAMINATION-2009 COMPUTER ARCHITECTURE & ORGANIZATION FULL MARK: 70 TIME: - 3HOURS Prepared by Asst.Prof S.K.Rath (CSE DEPARTMENT) Page 6 it can run different processes (or different threads belonging to the same process) on different CPUs. Multiprocessing is the use of two or more central processing units (CPUs) within a single computer system. The term also refers to the ability of a system to support more than one processor and/or the ability to allocate tasks between them.[1] There are many variations on this basic theme, and the definition of multiprocessing can vary with context, mostly as a function of how CPUs are defined (multiple cores on one die, multiple chips in one package, multiple packages in one system unit, etc.). 5) A) write an algorithm for signed operand multiplication using booth algorithm. Ans: Register used in Booths algorithm: A->Accumulator (initially Zero) M-> Multiplicand Q-> Multiplier SC -> Sequential Counter (No’s of bits present in Q Register)
  7. 7. GANDHI INSTITUTE FOR EDUCATION & TECHNOLOGY FIFT SEMESTER EXAMINATION-2009 COMPUTER ARCHITECTURE & ORGANIZATION FULL MARK: 70 TIME: - 3HOURS Prepared by Asst.Prof S.K.Rath (CSE DEPARTMENT) Page 7 This process is continuing till the sequential counter becomes Zero. The result is stored in Register A and Q. Example: B) What is cache? Why it is required in a computer system? Can cache replaced by cache? Ans: Cache (pronounced cash) memory is extremely fast memory that is built into a computer’s central processing unit (CPU), or located next to it on a separate chip. The CPU uses cache memory to store instructions that are repeatedly required to run programs, improving overall system speed. The advantage of cache memory is that the CPU does not have to use the motherboard’s system bus for data transfer. Whenever data must be passed through the system bus, the data transfer speed slows to the motherboard’s capability. The CPU can process data much faster by avoiding the bottleneck created by the system bus.
  8. 8. GANDHI INSTITUTE FOR EDUCATION & TECHNOLOGY FIFT SEMESTER EXAMINATION-2009 COMPUTER ARCHITECTURE & ORGANIZATION FULL MARK: 70 TIME: - 3HOURS Prepared by Asst.Prof S.K.Rath (CSE DEPARTMENT) Page 8 No , cache cannot replaced by RAM because we are using cache for adjustment of speed mismatch between processor and main memory. 6 A) what do you mean by addressing mode? Discuss different type of addressing mode. Addressing modes are an aspect of the instruction set architecture in most central processing unit (CPU) designs. The various addressing modes that are defined in a given instruction set architecture define how machine language instructions in that architecture identify the operand (or operands) of each instruction. An addressing mode specifies how to calculate the effective memory address of an operand by using information held in registers and/or constants contained within a machine instruction or elsewhere. Types of Addressing Modes Each instruction of a computer specifies an operation on certain data. The are various ways of specifying address of the data to be operated on. These different ways of specifying data are called the addressing modes. The most common addressing modes are:  Immediate addressing mode  Direct addressing mode  Indirect addressing mode  Register addressing mode  Register indirect addressing mode  Displacement addressing mode  Stack addressing mode To specify the addressing mode of an instruction several methods are used. Most often used are: a) Different operands will use different addressing modes. b) One or more bits in the instruction format can be used as mode field. The value of the mode field determines which addressing mode is to be used. The effective address will be either main memory address of a register. Immediate Addressing: This is the simplest form of addressing. Here, the operand is given in the instruction itself. This mode is used to define constant or set initial values of variables. The advantage of this mode is that no memory reference other than instruction fetch is required to obtain operand. The disadvantage is that the size of the number is limited to the size of the address field, which most instruction sets is small compared to word length. INSTRUCTION OPERAND Direct Addressing: In direct addressing mode, effective address of the operand is given in the address field of the instruction. It requires one memory reference to read the operand from the given location and provides only a limited address space. Length of the address field is usually less than the word length.
  9. 9. GANDHI INSTITUTE FOR EDUCATION & TECHNOLOGY FIFT SEMESTER EXAMINATION-2009 COMPUTER ARCHITECTURE & ORGANIZATION FULL MARK: 70 TIME: - 3HOURS Prepared by Asst.Prof S.K.Rath (CSE DEPARTMENT) Page 9 Ex : Move P, Ro, Add Q, Ro P and Q are the address of operand. Indirect Addressing: Indirect addressing mode, the address field of the instruction refers to the address of a word in memory, which in turn contains the full length address of the operand. The advantage of this mode is that for the word length of N, an address space of 2N can be addressed. He disadvantage is that instruction execution requires two memory reference to fetch the operand Multilevel or cascaded indirect addressing can also be used. Register Addressing: Register addressing mode is similar to direct addressing. The only difference is that the address field of the instruction refers to a register rather than a memory location 3 or 4 bits are used as address field to reference 8 to 16 generate purpose registers. The advantages of register addressing are Small address field is needed in the instruction. Register Indirect Addressing: This mode is similar to indirect addressing. The address field of the instruction refers to a register. The register contains the effective address of the operand. This mode uses one memory reference to obtain the operand. The address space is limited to the width of the registers available to store the effective address. Displacement Addressing: In displacement addressing mode there are 3 types of addressing mode. They are: 1) Relative addressing 2) Base register addressing 3) Indexing addressing. This is a combination of direct addressing and register indirect addressing. The value contained in one address field. A is used directly and the other address refers to a register whose contents are added to A to produce the effective address. Stack Addressing: Stack is a linear array of locations referred to as last-in first out queue. The stack is a reserved block of location, appended or deleted only at the top of the stack. Stack pointer is a register which stores the address of top of stack location. This mode of addressing is also known as implicit addressing. 7) What do you mean by BUS? What are the different buses present in a computer system? Ans: Bus: - Bus is a transmission medium which is used to transfer the data or information from one device to other device. There are three types of bus. There are three types of bus: 1. Address Bus 2. Data Bus 3. Control Bus.
  10. 10. GANDHI INSTITUTE FOR EDUCATION & TECHNOLOGY FIFT SEMESTER EXAMINATION-2009 COMPUTER ARCHITECTURE & ORGANIZATION FULL MARK: 70 TIME: - 3HOURS Prepared by Asst.Prof S.K.Rath (CSE DEPARTMENT) Page 10 Control Bus: The control bus is used by the CPU to direct and monitor the actions of the other functional areas of the computer. It is used to transmit a variety of individual signals (read, write, interrupt, acknowledge, and so forth) necessary to control and coordinate the operations of the computer. The individual signals transmitted over the control bus and their functions are covered in the appropriate functional area description. Address Bus: The address bus consists of all the signals necessary to define any of the possible memory address locations within the computer, or for modular memories any of the possible memory addresses locations within a module. An address is defined as a label, symbol, or other set of characters used to designate a location or register where information is stored. Before data or instructions can be written into or read from memory by the CPU or I/O sections, an address must be transmitted to memory over the address bus. Data Bus: The bidirectional data bus, sometimes called the memory bus, handles the transfer of all data and instructions between functional areas of the computer. The bidirectional data bus can only transmit in one direction at a time. The data bus is used to transfer instructions from memory to the CPU for execution. It carries data (operands) to and from the CPU and memory as required by instruction translation. The data bus is also used to transfer data between memory and the I/O section during input/output operations. The information on the data bus is either written into. 8 A) write short notes on any two. a) Booth’s algorithm b) Memory Interfacing c) Daisy Chain Method Ans: a) Booth’s algorithm: Booth's multiplication algorithm is a multiplication algorithm that multiplies two signed binary numbers in two's complement notation.
  11. 11. GANDHI INSTITUTE FOR EDUCATION & TECHNOLOGY FIFT SEMESTER EXAMINATION-2009 COMPUTER ARCHITECTURE & ORGANIZATION FULL MARK: 70 TIME: - 3HOURS Prepared by Asst.Prof S.K.Rath (CSE DEPARTMENT) Page 11 b) Memory Interfacing: While executing a program, the microprocessor needs to access memory frequently to read instruction codes and data stored in memory and the interfacing circuit enables that access. The primary function of memory interfacing is to allow the microprocessor to read from and write into a given register of memory chip. 1. Be able to select the chip 2. Identify the register 3. Enable the appropriate buffer. c) Daisy-Chain method: This is a method in which the bus request (BR) signal of all bus forms online. - The bus busy (BB) output of all forms another one line bus. - When no bus is using the bus, BB is inactive. - Whenever one or more bus request is present, the BR signal will active. - It is low cost techniques. - The priority for a bus depends on its proximity to bus grant signal.

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