Future of teaching VHDL

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What if students would know all of the VHDL syntax? What if VHDL tools would not freak out about a simple error in the code? Sigasi makes this possible!

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Future of teaching VHDL

  1. 1. The future ofteaching VHDL
  2. 2. What if studentswould... The future of teaching VHDL
  3. 3. know all packages The future of teaching VHDL 3
  4. 4. know the syntaxThe future of teaching VHDL 4
  5. 5. know the syntaxThe future of teaching VHDL 5
  6. 6. know all declarations The future of teaching VHDL 6
  7. 7. know record fieldsThe future of teaching VHDL 7
  8. 8. know record fieldsThe future of teaching VHDL 8
  9. 9. What if tools ... The future of teaching VHDL 9
  10. 10. for one single error The future of teaching VHDL 10
  11. 11. would not freak outModel Technology ModelSim ALTERA vcom 6.4a Compiler 2008.08 Oct 222008-- Loading package standard-- Loading package std_logic_1164-- Compiling package p** Error: p.vhd(6): near ";": expecting "RECORD"** Error: p.vhd(7): (vcom-1136) Unknown identifier "c1".** Error: p.vhd(7): Aggregate expression cannot be scalar type(error).** Error: p.vhd(9): Invalid expanded name prefix (selected name).** Error: p.vhd(11): VHDL Compiler exiting The future of teaching VHDL 11
  12. 12. but yieldone single message The future of teaching VHDL 12
  13. 13. and 4 messages for 4 errorsThe future of teaching VHDL 13
  14. 14. Wouldn’t that be great? The future of teaching VHDL
  15. 15. Students could• write correct code,• get immediate feedback,• with sensible error messages,• feel the code,• concentrate on concepts, not syntax. The future of teaching VHDL 15
  16. 16. Teachers could• teach engineering, not languages,• not waste time on tooling,• deliver even better graduates. The future of teaching VHDL 16
  17. 17. The future is now.and it’s free too! The future of teaching VHDL 17
  18. 18. free educational licenses at www.sigasi.com

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