《Arm应用系统开发详解——基于s3 c4510b的系统设计(第二版)》

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《Arm应用系统开发详解——基于s3 c4510b的系统设计(第二版)》

  1. 1. ARM S3C4510B 1ARM S3C4510B 2004 6 2006 6
  2. 2. ARM S3C4510B 2 16/32 RISC ARM ARMSamsung ARM S3C4510B ARM ARM ARM 16/32
  3. 3. ARM S3C4510B 3
  4. 4. ARM S3C4510B 4
  5. 5. ARM S3C4510B 51 ARM ........................................................................................................ 71.1 ARM Advanced RISC Machines ................................................................................... 71.2 ARM .................................................................................. 71.3 ARM .......................................................................................................... 81.4 ARM ........................................................................................................ 121.5 ARM ............................................................................................ 131.6 ......................................................................................................................... 152 ARM .......................................................................................... 162.1 ARM ............................................................................................ 162.2 ARM ........................................................................................ 172.3 ..................................................................................................... 182.4 ..................................................................................................................... 182.5 ..................................................................................................................... 182.6 Exceptions ....................................................................................................... 252.7 ......................................................................................................................... 303 ARM .......................................................................................... 313.1 ARM ........................................................................................ 313.2 ARM .................................................................................................... 333.3 ARM ................................................................................................................... 353.4 Thumb ......................................................................................................... 523.5 ......................................................................................................................... 524 ARM ...................................................................................................... 534.1 ARM ........................................................................................ 534.2 ..................................................................................................... 644.3 ..................................................................................................... 684.4 ......................................................................................................... 734.5 ......................................................................................................................... 785 .................................................................................................... 795.1 ................................................................................................................. 795.2 S3C4510B ............................................................................................................... 81
  6. 6. ARM S3C4510B 65.3 ............................................................................... 1095.4 ........................................................................................................... 1405.5 ....................................................................................... 1465.6 ....................................................................................................................... 1486 .......................................................................................... 1496.1 ....................................................................................... 1496.2 ........................................................................................... 1506.3 BootLoader ............................................................................................................ 2286.4 ....................................................................................................................... 2327 uClinux .................................................................................. 2337.1 uClinux .............................................................................................. 2337.2 GNU .................................................................................................. 2367.3 uClinux .................................................................................................. 2497.4 uClinux .......................................................................................... 2587.5 uClinux .................................................................................. 2837.6 ....................................................................................................................... 2938 ARM ADS ......................................................................... 2948.1 ADS ....................................................................................... 2948.2 ADS ....................................................................................................... 3118.3 AXD .................................................................................................. 3228.4 ....................................................................................................................... 326 A ..................................................................................................................... 327 B ..................................................................................................................... 328
  7. 7. ARM S3C4510B 7 1 ARM1.1 ARM Advanced RISC Machines ARM Advanced RISC Machines 1990 ARM ARM IP ARM ARM 32 RISC 75 ARM ARM RISC ARM ARM ARM ARM ARM1.2 ARM1.2.1 ARM ARM 1 32 RISC ARM ARM
  8. 8. ARM S3C4510B 8 8 /16 2 85% ARM ARM 3 ARM ADSL ARM DSP 4 ARM 5 ARM 32 SIM ARM ARM1.2.2 ARM RISC ARM 1 2 Thumb 16 /ARM 32 3 4 5 61.3 ARM ARM ARM ARM ARM ARM7 ARM9 ARM9E ARM10E ARM11 SecurCore Inter StrongARM Xscale ARM7 ARM9 ARM9E ARM10 4 SecurCore
  9. 9. ARM S3C4510B 91.3.1 ARM7 ARM7 32 RISC ARM7 ICE RT 0.9MIPS/MHz 3 16 Thumb Windows CE Linux Palm OS ARM9 ARM9E ARM10E 130MIPS ARM7 Internet ARM7 ARM7TDMI ARM7TDMI-SARM720T ARM7EJ ARM7TDMI 32 RISC ARM TDMI T 16 Thumb D Debug M Multiplier I ICE Samsung S3C4510B1.3.2 ARM9 ARM9 5 1.1MIPS/MHz 32 ARM 16 Thumb 32 AMBA MMU Windows CE Linux Palm OS MPU Cache Cache ARM9
  10. 10. ARM S3C4510B 10 ARM9 ARM920T ARM922T ARM940T1.3.3 ARM9E ARM9E DSPJava ARM9E DSP DSP ARM9E DSP 5 32 ARM 16 Thumb 32 AMBA VFP9 MMU Windows CE Linux Palm OS MPU Cache Cache 300MIPS ARM9 ARM9E ARM926EJ-S ARM946E-S ARM966E-S1.3.4 ARM10E ARM10E ARM9 50 ARM10E ARM10E DSP 6 32 ARM 16 Thumb 64 AMBA VFP10 MMU Windows CE Linux Palm OS Cache Cache 400MIPS
  11. 11. ARM S3C4510B 11 / ARM10E ARM10E ARM1020E ARM1022E ARM1026EJ-S1.3.5 ARM11 ARM 2003 4 29 ARM CPU ARM11Jaguar ARM11 ARM11 0.13 350MHz 500MHz 533 750MHz 0.10 1GHz ARM7 ARM9 400MHzIntel Xscale 500MHz1.3.6 SecurCore SecurCore 32 RISC SecurCore ARM SecurCore ARM SecurCore SecurCore SecurCore SC100 SecurCore SC110 SecurCore SC200 SecurCore SC2101.3.7 StrongARM Xscale Intel StrongARM SA-1100 ARM 32 RISC Inter ARM ARMv4 Intel Intel StrongARM StrongARM Xscale ARMv5TE
  12. 12. ARM S3C4510B 12 16 Thumb DSP Intel 2006 XscaleXscale1.4 ARM1.4.1 RISC CISC Complex Instruction Set Computer CISC 20 80 80 20 1979 RISC ReducedInstruction Set Computer RISC RISC RISC RISC 2 3 / ARM / CISC RISC RISC CISC RISC CISC CPU CISC RISC CPU
  13. 13. ARM S3C4510B 13RISC CISC CPU1.4.2 ARM ARM 37 32 31 PC 32 6 CPU 32 ARM 7 15 R0 R14 1 2 7 ARM1.4.3 ARM ARM ARM Thumb ARM 32 Thumb 16 Thumb ARM ARM 30 40 32 ARM1.5 ARM ARM ARM ARM ARM ARM ARM Windows CE Linux ARM720T MMU Memory Management Unit ARMARM720T ARM920T ARM922T ARM946T Xscale MMU ARM7TDMI MMU Windows CE Linux uCLinux RTLinux uC/OSII
  14. 14. ARM S3C4510B 14 MMU ARM7TDMI MMU S3C4510B MMU ARMuCLinux RTLinux uC/OSII MMU ARM ARM7 0.9MIPS/MHz ARM7 20MHz 133MHzARM9 1.1MIPS/MHz ARM9150MHz 233MHz ARM10 750MHz ARMARM9 ARM10 ARM7 ARM7 ARM7 ARM ATMEL AT91F40162 2MB ARM ARM USB IIS LCD RTC ADC DAC DSP ARM ARM ARM Samsung Atmel TI Intel Cirrus Logic Motorola ARM
  15. 15. ARM S3C4510B 151.6 ARM ARM ARM ARM ARM
  16. 16. ARM S3C4510B 16 2 ARM2.1 ARM
  17. 17. ARM S3C4510B 172.2 ARM
  18. 18. ARM S3C4510B 182.32.42.5
  19. 19. ARM S3C4510B 192.5.1 ARM R13_<mode> R14_<mode>
  20. 20. ARM S3C4510B 20MOV PC LRBX LR STMFD SP ,{<Regs>,LR} LDMFD SP ,{<Regs>,PC} ARM ARM PC PC 8
  21. 21. ARM S3C4510B 21 R16 CPSR(Current Program Status Register ) CPSR2.5.2 Thumb
  22. 22. ARM S3C4510B 22
  23. 23. ARM S3C4510B 232.5.3
  24. 24. ARM S3C4510B 24 2-1
  25. 25. ARM S3C4510B 25 2-2 M[4 0] M[4 0] 0b10000 PC CPSR,R0-R14 0b10001 FIQ PC CPSR, SPSR_fiq R14_fiq-R8_fiq, R7 R0 0b10010 IRQ PC CPSR, SPSR_irq R14_irq,R13_irq,R12 R0 0b10011 PC CPSR, SPSR_svc R14_svc,R13_svc,,R12 R0, 0b10111 PC CPSR, SPSR_abt R14_abt,R13_abt, R12 R0, 0b11011 PC CPSR, SPSR_und R14_und,R13_und, R12 R0, 0b11111 PC CPSR ARM v4 , R14 R0 2-22.6 Exceptions
  26. 26. ARM S3C4510B 262.6.1 ARM 2-3 ARM ARM SWI IRQ CPSR I 0 IRQ FIQ CPSR F 0 FIQ2.6.2 R14_<Exception_Mode> = Return Link SPSR_<Exception_Mode> = CPSR
  27. 27. ARM S3C4510B 27 CPSR[4:0] = Exception Mode Number CPSR[5] = 0 ARM If <Exception_Mode> == Reset or FIQ then FIQ FIQ CPSR[6] = 1 CPSR[7] = 1 PC = Exception Vector Address2.6.32.6.4 SUBS PC,R14_fiq ,#4 R14_fiq 4 PC SPSR_mode CPSR SUBS PC , R14_irq , #4 R14_irq 4 PC SPSR_mode CPSR
  28. 28. ARM S3C4510B 28 SUBS PC, R14_abt, #4 SUBS PC, R14_abt, #8 MOV PC , R14_svc MOVS PC, R14_und2.6.5 / 2-4 R14 PC 2-4 / ARM R14_x Thumb R14_x BL MOV PC R14 PC 4 PC 2 1 SWI MOVS PC R14_svc PC 4 PC 2 1
  29. 29. ARM S3C4510B 29 UDEF MOVS PC R14_und PC 4 PC 2 1 FIQ SUBS PC R14_fiq 4 PC 4 PC 4 2 IRQ SUBS PC R14_irq 4 PC 4 PC 4 2 PABT SUBS PC R14_abt 4 PC 4 PC 4 1 DABT SUBS PC R14_abt 8 PC 8 PC 8 3 RESET NA 4 1 PC BL/SWI/ 2 PC FIQ IRQ 3 PC 4 R14_svc2.6.6 Exception Vectors 2-5 0x0000,0000 0x0000,0004 0x0000,0008 0x0000,000C 0x0000,0010 0x0000,0014 0x0000,0018 IRQ IRQ 0x0000,001C FIQ FIQ2.6.7 Exception Priorities 2-6 1 2 3 FIQ 4 IRQ 5 6 SWI
  30. 30. ARM S3C4510B 302.6.8 ARM ARM PC2.7 ARM ARM ARM Banked 8/16 X86
  31. 31. ARM S3C4510B 31 3 ARM3.1 ARM3.1.1 ARM 3-1 ARM ADC ADD AND B BIC BL BLX BX CDP CMN CMP EOR LDC
  32. 32. ARM S3C4510B 32 LDM LDR MCR ARM MLA MOV MRC ARM MRS CPSR SPSR MSR CPSR SPSR MUL 32 MLA 32 MVN ORR RSB RSC SBC STC STM STR SUB SWI SWP TEQ TST3.1.2 ARM CPSR ARM 4 4 [31:28] 16 B EQ BEQ CPSR Z 16 15 3-2 16 1111 3-2 0000 EQ Z 0001 NE Z 0010 CS C
  33. 33. ARM S3C4510B 33 0011 CC C 0100 MI N 0101 PL N 0110 VS V 0111 VC V 1000 HI C Z 1001 LS C Z 1010 GE N V 1011 LT N V 1100 GT Z N V 1101 LE Z N V 1110 AL3.2 ARMARM3.2.1 ADD R0 R0 1 R0 ADD R0 R0 0x3f R0 0x &3.2.2 ADD R0 R1 R2 R0 R1 R2 R03.2.3
  34. 34. ARM S3C4510B 34 ADD R0 R1 [R2] R0 R0 R0 R2 R1 R0 R1 R0 R0 R13.2.4 LDR R0 [R1 4] R0 LDR R0 [R1 4] R0 LDR R0 [R1] 4 R0 LDR R0 [R1 R2] R0 R1 4 R0 R1 4 R0 R1 4 R1 R0 R1 4 R1 R2 R03.2.5 16 LDMIA R0 {R1 R2 R3 R4} R1 R2 R3 R4 IA / R0 R1 R43.2.6 PC
  35. 35. ARM S3C4510B 35 BL BL NEXT NEXT3.2.7 First In Last Out FILO Full Stack Empty Stack Ascending Stack Decending Stack ARM3.3 ARM ARM3.3.1 ARM PC PC 4GB MOV LR PC
  36. 36. ARM S3C4510B 36 4GBARM 32MB 4 B B Label Label CMP R1 0 CPSR Z Label BEQ Label BL Label Label PC R14
  37. 37. ARM S3C4510B 373.3.2 MOV R1 R0 R0 R1 MOV PC R14 R14 PC MOV R1 R0 LSL 3 R0 3 R1
  38. 38. ARM S3C4510B 38MVN R0 0 0 R0 R0=-1CMP R1 R0 R1 R0 CPSRCMP R1 100 R1 100 CPSRCMN R1 R0 R1 R0 CPSRCMN R1 100 R1 100 CPSRTST R1 1 R1TST R1 0xffe R1 0xffe CPSR
  39. 39. ARM S3C4510B 39TEQ R1 R2 R1 R2 CPSR 1 2ADD R0 R1 R2 R0 = R1 + R2ADD R0 R1 #256 R0 = R1 + 256ADD R0 R2 R3 LSL#1 R0 = R2 + (R3 << 1)ADDS R0 R4 R8ADCS R1 R5 R9ADCS R2 R6 R10ADC R3 R7 R11 1 2 1 2
  40. 40. ARM S3C4510B 40 SUB R0 R1 R2 R0 = R1 - R2 SUB R0 R1 #256 R0 = R1 - 256 SUB R0 R2 R3 LSL#1 R0 = R2 - (R3 << 1) 1 2 1 2 32 SUBS R0 R1 R2 R0 = R1 - R2 - C CPSR 2 1 1 2 RSB R0 R1 R2 R0 = R2 – R1 RSB R0 R1 #256 R0 = 256 – R1 RSB R0 R2 R3 LSL#1 R0 = (R3 << 1) - R2 2 1 1 2 32 RSC R0 R1 R2 R0 = R2 – R1 - C1 2 1
  41. 41. ARM S3C4510B 41 AND R0 R0 3 R0 0 11 2 1 ORR R0 R0 3 R0 0 1 1 2 1 EOR R0 R0 3 R0 0 1 1 1 2 2 32 BIC R0 R0 1011 R0 0 1 33.3.3 ARM 6 32 64 1 6
  42. 42. ARM S3C4510B 42 CPSR 1 2 32 MUL R0 R1 R2 R0 = R1 R2 MULS R0 R1 R2 R0 = R1 R2 CPSR CPSR1 2 32 MLA R0 R1 R2 R3 R0 = R1 R2 + R3 MLAS R0 R1 R2 R3 R0 = R1 R2 + R3 CPSR 32 Low 32 High CPSR 1 2 32 SMULL R0 R1 R2 R3 R0 = R2 R3 32 R1 = R2 R3 32 32 Low Low 32 High High CPSR 1 2 32
  43. 43. ARM S3C4510B 43 SMLAL R0 R1 R2 R3 R0 = R2 R3 32 R0 R1 = R2 R3 32 R1 32 Low 32 High CPSR 1 2 32 UMULL R0 R1 R2 R3 R0 = R2 R3 32 R1 = R2 R3 32 32 Low Low 32 High High CPSR 1 2 32 UMLAL R0 R1 R2 R3 R0 = R2 R3 32 R0 R1 = R2 R3 32 R13.3.4 ARM
  44. 44. ARM S3C4510B 44 MRS MRS R0 CPSR CPSR R0 MRS R0 SPSR SPSR R0 MSR CPSR R0 R0 CPSR MSR SPSR R0 R0 SPSR MSR CPSR_c R0 R0 SPSR CPSR3.3.5 / ARM /
  45. 45. ARM S3C4510B 45LDR R0 [R1] R1 R0LDR R0 [R1 R2] R1+R2 R0LDR R0 [R1 8] R1+8 R0LDR R0 [R1 R2] R1+R2 R0 R1 R2 R1LDR R0 [R1 8] R1+8 R0 R1 8 R1LDR R0 [R1] R2 R1 R0 R1 R2 R1LDR R0 [R1 R2 LSL 2] R1 R2 4 R0 R1 R2 4 R1LDR R0 [R1] R2 LSL 2 R1 R0 R1 R2 4 R1LDRB R0 [R1] R1 R0 R0 24LDRB R0 [R1 8] R1 8 R0 R024
  46. 46. ARM S3C4510B 46 LDRH R0 [R1] R1 R0 R0 16 LDRH R0 [R1 8] R1 8 R0 R0 16 LDRH R0 [R1 R2] R1 R2 R0 R0 16 STR R0 [R1] 8 R0 R1 R1 8 R1 STR R0 [R1 8] R0 R1 8 STRB R0 [R1] R0 R1 STRB R0 [R1 8] R0 R1 8 STRH R0 [R1] R0 R1 STRH R0 [R1 8] R0 R1 83.3.6 / ARM /
  47. 47. ARM S3C4510B 47 STMFD R13! {R0 R4-R12 LR} R0 R4 R12 LR LDMFD R13! {R0 R4-R12 PC} R0 R4 R12 LR3.3.7 ARM
  48. 48. ARM S3C4510B 48 SWP R0 R1 [R2] R2 R0 R1 R2 SWP R0 R0 [R1] R1 R0 SWPB R0 R1 [R2] R2 R0 R0 24 R1 8 R2 SWPB R0 R0 [R1] R1 R0 83.3.8 LSL ASL LSR ASR ROR RRX LSL ASL 0 31 MOV R0, R1, LSL#2 R1 R0
  49. 49. ARM S3C4510B 49 LSR 0 31 MOV R0, R1, LSR#2 R1 R0 ASR 31 0 31 MOV R0, R1, ASR#2 R1 R0 31 ROR 0 31 32 MOV R0, R1, ROR#2 R1 R0 RRX C 0 31 MOV R0, R1, RRX#2 R1 R03.3.9 ARM 16 ARM ARM ARM ARM ARM ARM
  50. 50. ARM S3C4510B 50 ARM 5CDP P3 2 C12 C10 C3 4 P3LDC P3 C4 [R0] ARM R0 P3 C4STC P3 C4 [R0] P3 C4 ARM R0
  51. 51. ARM S3C4510B 51 MCR P3 3 R0 C4 C5 6 ARM R0 P3 C4 C5 MRC P3 3 R0 C4 C5 6 P3 ARM3.3.10 ARM SWI 0x02 02
  52. 52. ARM S3C4510B 523.4 Thumb ARM 32 ARM 16Thumb Thumb ARM 16 32 Thumb 32 Thumb ARM Thumb ARM Thumb ARM ARM ARM ARM Thumb ARM Thumb ARM Thumb 32 32 Thumb 16 ARM Thumb ARM Thumb Thumb 16 ARM Thumb ARM Thumb ARM ARM Thumb 32 ARM 16 Thumb3.5 ARM X86 ARM Thumb ARM ARM Thumb ARM
  53. 53. ARM S3C4510B 53 4 ARM4.1 ARM ARM ARM4.1.1 Symbol Definition ARM GBLA GBLL GBLS LCLA LCLL LCLS SETA SETL SETS RLIST GBLA GBLL GBLS GBLA GBLL GBLS ARM
  54. 54. ARM S3C4510B 54GBLA 0GBLL FGBLS GBLA Test1 Test1 Test1 SETA 0xaa 0xaa GBLL Test2 Test2 Test2 SETL {TRUE} GBLS Test3 Test3 Test3 SETS Testing TestingLCLA LCLL LCLSLCLA LCLL LCLS ARMLCLA 0LCLL FLCLS LCLA Test4 Test4 Test3 SETA 0xaa 0xaa LCLL Test5 Test5 Test4 SETL {TRUE} LCLS Test6 Test6 Test6 SETS Testing Testing SETA SETL SETS SETA SETL SETSSETASETLSETS LCLA Test3 Test3 Test3 SETA 0xaa 0xaa LCLL Test4 Test4
  55. 55. ARM S3C4510B 55 Test4 SETL {TRUE}4 RLIST RLIST { } RLISTARM LDM/STM LDM/STM RegList RLIST {R0-R5 R8 R10} RegList ARM LDM/STM4.1.2 Data Definition DCB DCW DCWU DCD DCDU DCFD DCFDU DCFS DCFSU DCQ DCQU 8 SPACE MAP FIELD DCB DCB 0 255 DCB = Str DCB This is a test DCW DCWU DCW DCWU
  56. 56. ARM S3C4510B 56 DCW DCWU DataTest DCW 1 2 3 DCD DCDUDCD DCDU DCD & DCD DCDU DataTest DCD 4 5 6 DCFD DCFDUDCFD DCFDU DCFD DCFDU FDataTest DCFD 2E115 -5E7 DCFS DCFSUDCFS DCFSU DCFS DCFSU FDataTest DCFS 2E5 -5E 7 DCQ DCQUDCQ DCQU 8
  57. 57. ARM S3C4510B 57 DCQ DCQU DataTest DCQ 100 SPACE SPACE 0 SPACE DataSpace SPACE 100 100 0 MAP { } MAP MAP MAP FIELD MAP 0x100 R0 0x100 R0 FIELD FIELD FILED # FIELD MAP MAP FIELD MAP FIELD MAP 0x100 0x100 A FIELD 16 A 16 0x100 B FIELD 32 B 32 0x110 S FIELD 256 S 256 0x1304.1.3 Assembly Control
  58. 58. ARM S3C4510B 58 IF ELSE ENDIF WHILE WEND MACRO MEND MEXIT IF 1 ELSE 2 ENDIF IF ELSE ENDIF IF 1 2 ELSE 2 IF 1 IF ELSE ENDIF GBLL Test Test IF Test = TRUE 1 ELSE 2 ENDIF WHILE WEND WHILE WENDWHILE WHILE WEND GBLA Counter Counter WHILE Counter < 10
  59. 59. ARM S3C4510B 59 WEND $ $ 1 $ 2 MEND MACRO MEND $ MACRO MEND MACRO MEND MEXIT MEXIT4.1.4 AREA ALIGN CODE16 CODE32 ENTRY END EQU EXPORT GLOBAL IMPORT EXTERN GET INCLUDE INCBIN
  60. 60. ARM S3C4510B 60 RN ROUTAREA 1 2AREA| |1_test| CODE READONLY DATA READWRITE READONLY READONLY READWRITE READWRITE ALIGN ALIGN ELF 0 31 2 COMMON COMMON AREA Init CODE READONLY InitALIGN { { }}ALIGN | 2 1 2 4 8 16 2 AREA Init CODE READONLY ALIEN 3 8 ENDCODE16 CODE32
  61. 61. ARM S3C4510B 61 CODE16 16 Thumb CODE32 32 ARM ARM Thumb CODE16 16 Thumb CODE32 32 ARM ARM Thumb AREA Init CODE READONLY CODE32 32 ARM LDR R0 NEXT 1 R0 BX R0 Thumb 16 Thumb ENTRY ENTRYENTRY ENTRY ENTRY AREA Init CODE READONLY ENTRY END END AREA Init CODE READONLY END EQU { }
  62. 62. ARM S3C4510B 62 EQU C define EQU * EQU 32 CODE16 CODE32 DATA Test EQU 50 Test 50 Addr EQU 0x55 CODE32 Addr 0x55 32 ARM EXPORT {[WEAK]} EXPORTEXPORT GLOBAL [WEAK] AREA Init CODE READONLY END IMPORT {[WEAK]} IMPORT [WEAK] 0 B BL B BL NOP AREA Init CODE READONLY END EXTERN {[WEAK]} EXTERN
  63. 63. ARM S3C4510B 63 [WEAK] 0 B BL B BL NOP AREA Init CODE READONLY ENDGETGET INCLUDE GET EQUMAP FIELD GET C includeGET INCBIN AREA Init CODE READONLY ENDINCBININCBIN AREA Init CODE READONLY END RNRN
  64. 64. ARM S3C4510B 64 { } ROUT ROUT AREA ROUT ROUT ROUT4.2 ARM Thumb { } { } { } 4.2.1 ARM Thumb ARM Thumb GBLA GBLL GBLS LCLA LCLL LCLS SETA SETL
  65. 65. ARM S3C4510B 65SETS ARM Thumb 32 0 232-1 -231 231-1 $ $ $ $ $ $4.2.2 / MOD X Y X Y X Y
  66. 66. ARM S3C4510B 66X Y X YX Y X YX/Y X YX MOD Y X Y ROL ROR SHL SHR X YX ROL Y X YX ROR Y X YX SHL Y X YX SHR Y X Y AND OR NOT EOR X YX AND Y X YX OR Y X Y NOT Y YX EOR Y X Y = > < >= <= /= <> X YX=Y X YX>Y X YX<Y X YX >= Y X YX <= Y X YX /= Y X YX <> Y X Y LAND LOR LNOT LEOR X YX LAND Y X YX LOR Y X Y LNOT Y YX LEOR Y X Y 512 LEN
  67. 67. ARM S3C4510B 67 LEN X LEN X CHR CHR 0 255 M CHR M STR STRSTR STR T F STR X X LEFT LEFT X LEFT Y X Y RIGHT LEFT RIGHT X RIGHT Y X Y CC CC X CC Y X 1 Y 2 CC Y X PC BASE BASE BASE X X INDEX INDEX INDEX X X
  68. 68. ARM S3C4510B 68 ?X X DEF DEF DEF X X4.34.3.1 ARM Thumb AREA Init CODE READONLY ENTRY Start LDR R0 =0x3FF5000 LDR R1 0xFF STR R1 [R0] LDR R0 =0x3FF5008 LDR R1 0x01 STR R1 [R0] ... END AREA Init ENTRY END
  69. 69. ARM S3C4510B 69 END4.3.2 ARM BL BL LR PC LR PC R0 R3 BL AREA Init CODE READONLY ENTRY Start LDR R0 =0x3FF5000 LDR R1 0xFF STR R1 [R0] LDR R0 =0x3FF5008 LDR R1 0x01 STR R1 [R0] BL PRINT_TEXTPRINT_TEXT ... END4.3.3 S3C4510B S3C4510B;***************************************************************************;Institute of Automation,Chinese Academy of Sciences;Description: This example shows the UART communication;Author: Li Juguang;Date:;***************************************************************************;***********************************;Define Special Function Register
  70. 70. ARM S3C4510B 70;***********************************IOPMOD EQU 0x3FF5000IOPDATA EQU 0x3FF5008UARTLCON0 EQU 0x3FFD000UARTCONT0 EQU 0x3FFD004UARTSTAT0 EQU 0x3FFD008UTXBUF0 EQU 0x3FFD00CUARTBRD0 EQU 0x3FFD014 AREA Init,CODE,READONLY ENTRY;**************************************************;LED Display;************************************************** LDR R1,=IOPMOD LDR R0,=&ff STR R0,[R1] LDR R1,=IOPDATA LDR R0,=&ff STR R0,[R1];*************************************************;UART0 line control register;************************************************* LDR R1,=UARTLCON0 LDR R0,=0x03 STR R0,[R1];**************************************************;UART0 control regiser;************************************************** LDR R1,=UARTCONT0 LDR R0,=0x9 STR R0,[R1];**************************************************;UART0 baud rate divisor regiser;Baudrate=19200 50MHz;*************************************************** LDR R1,=UARTBRD0 LDR R0,=0x500 STR R0,[R1];***************************************************;Print the messages!;***************************************************LOOP
  71. 71. ARM S3C4510B 71 LDR R0,=Line1 BL PrintLine LDR R0,=Line2 BL PrintLine LDR R0,=Line3 BL PrintLine LDR R0,=Line4 BL PrintLine LDR R1,=0x7FFFFFLOOP1 SUBS R1,R1,#1 BNE LOOP1 B LOOP;***************************************************;Print line;***************************************************PrintLine MOV R4,LR MOV R5,R0Line LDRB R1,[R5],#1 AND R0,R1,#&FF TST R0,#&FF MOVEQ PC,R4 BL PutByte B LinePutByte LDR R3,=UARTSTAT0 LDR R2,[R3] TST R2,#&40 BEQ PutByte LDR R3,=UTXBUF0 STR R0,[R3] MOV PC,LRLine1 DCB &A,&D,"******************************************************",0Line2 DCB &A,&D,"Chinese Academy of Sciences,Institute of Automation,ComplexSystem Lab.",0Line3 DCB &A,&D," ARM Development Board Based on Samsung ARM S3C4510B.",0Line4 DCB &A,&D,&A,&D,&A,&D,&A,&D,&A,&D,&A,&D,&A,&D,&A,&D,&A,&D,&A,&D,0 END
  72. 72. ARM S3C4510B 724.3.4 C/C++ ARM C/C++ C/C++ C/C++ C/C C/C C/C C/C C/C C/C 5 6;*************************************************************************;Institute of Automation, Chinese Academy of Sciences;File Name: Init.s;Description:;Author: Li Juguang;Date:;************************************************************************ IMPORT Main ; AREA Init,CODE,READONLY ENTRY LDR R0,=0x3FF0000 5 6 LDR R1,=0xE7FFFF80 STR R1,[R0] LDR SP,=0x3FE1000 BL Main Main C/C++ END Main C/C Main C main/**************************************************************************** Institute of Automation, Chinese Academy of Sciences* File Name: main.c
  73. 73. ARM S3C4510B 73* Description: P0,P1 LED flash.* Author: Li Juguang* Date:***************************************************************************/void Main(void){ int i; *((volatile unsigned long *) 0x3ff5000) = 0x0000000f; while(1) { *((volatile unsigned long *) 0x3ff5008) = 0x00000001; for(i=0; i<0x7fFFF; i++) ; *((volatile unsigned long *) 0x3ff5008) = 0x00000002; for(i=0; i<0x7FFFF; i++) ; }}4.4
  74. 74. ARM S3C4510B 744.4.14.4.2 · · AREA Init CODE READONLY ENTRY B Reset_Handler ;Reset_Handler B Undef_Handler B SWI_Handler B PreAbort_Handler B DataAbort_Handler B . ; B IRQ_Handler B FIQ_Handler Reset_Handler ...4.4.3
  75. 75. ARM S3C4510B 75 ARM 4GB MB4GB ARM Samsung S3C2410 Remap SamsungS3C4510B ARM Flash SDRAM PC 0x0 0x0 Flash ROM 0x0 Flash RAM Flash RAM0x0 0x0 Flash PC Flash Flash
  76. 76. ARM S3C4510B 76 RAM RAM Flash RAM Flash RAM RAM Flash PC4.4.4 MODEMASK EQU 0x1F FIQMODE EQU 0x11 IRQMODE EQU 0x12 SVCMODE EQU 0x13 SVCStack EQU 0x3FE0100 FIQStack EQU 0x3FE0200
  77. 77. ARM S3C4510B 77 IRQStack EQU 0x3FE0300 MRS R0,CPSR ;CPSR->R0 BIC R0,R0,#MODEMASK ; CPSR ORR R1,R0,#SVCMODE ; MSR CPSR_cxsf,R1 ; LDR SP,=SVCStack ; BIC R0,R0,#MODEMASK ; CPSR ORR R1,R0,#FIQMODE ; FIQ MSR CPSR_cxsf,R1 ; FIQ LDR SP,=FIQStack ; BIC R0,R0,#MODEMASK ; CPSR ORR R1,R0,#IRQMODE ; IRQ MSR CPSR_cxsf,R1 ; IRQ LDR SP,=IRQStack ;4.4.5 I/O4.4.6 C4.4.7
  78. 78. ARM S3C4510B 78 ARM ARM Thumb Thumb Thumb4.4.84.4.9 C IMPORT C_Entry main B C_Entry ARM ADS C IMPORT __main B __main __main( ) C main( ) main( ) main( ) main( ) main( ) main( )4.5
  79. 79. ARM S3C4510B 79 55.1 10MHz PLL 50MHz
  80. 80. ARM S3C4510B 80 Flash SDRAMSDRAM 10M/100M 10M 100Mbps JTAG IIC Real Time Clock RTC LED LCD ADC ARM DAC ARM CPLD
  81. 81. ARM S3C4510B 815.2 S3C4510B5.2.1 S3C4510B — — — — — — — — — — —
  82. 82. ARM S3C4510B 82——————————
  83. 83. ARM S3C4510B 83—————————————————————————————————
  84. 84. ARM S3C4510B 84————————————————————————————
  85. 85. ARM S3C4510B 85 —5.2.2 S3C4510B 5-1 S3C4510BXCLK 80 I CLKSEN PLL S3C4510B
  86. 86. ARM S3C4510B 86 CLKSEN XCLK S3C4510BMCLKO/SDCLK 77 O SDCLK SDRAMCLKSEL 83 I CLKSEL PLL S3C4510B CLKSEL XCLK S3C4510BnRESET 82 I ESET S3C4510B nRESET 64CLKOEN 76 ITMODE 63 IFILTER 55 AI PLL 820pFTCK 58 I JTAGTMS 59 I S3C4510B JTAGTDI 60 I JTAG S3C4510BTDO 61 O JTAG S3C4510BnTRST 62 I JTAGADDR[21:0]/ 117-110 O 22 ROM/ SRAMADDR[10]/AP 129-120 FLASH DRAM I/O 4M 135-132 16MXDATA[31:0] 141-136 I/O S3C4510B 8 154-144 16 32 166-159 175-169nRAS[3:0]/ 94,91, O S3C4510B 4 DRAMnSDCS[3:0] 90,89 nRAS nSDCS[3:0] SDRAMnCAS[3:0] 98,97, O DRAM 4nCAS[0] 96,95 nCAS nSDRAS/nSDRAS SDRAM nSDCAS SDRAMnCAS[1] CKE SDRAM/nSDCAS
  87. 87. ARM S3C4510B 87nCAS[2]/CKEnDWE 99 O DRAM nWBE[3:0] ROM/SRAM/FLASHnECS[3:0] 70,69, O 4 I/O 68,67 I/O 16KB nECS I/OnEWAIT 71 I I/O ,nRCS[5:0] 88-84,75 O S3C4510B 6 ROM/SRAM/FLASHB0SIZE[1:0] 74,73 I ROM/SRAM/FLASH 0 01 8 10 16 11 32 00nOE 72 OnWBE[3:0]/ 107, ODQM[3:0] 102-100 DRAM DRAM nCAS[3:0] nDWE DQM SDRAM /ExtMREQ 108 I S3C4510B ExtMACK S3C4510BExtMACK 109 OMDC 50 O MDIOMDIO 48 I/O PHYLITTLE 49 I S3C4510B S3C4510BCOL/COL_10M 38 ITX_CLK/ 46 I S3C4510B TX_CLKTXCLK_10M TXD[3:0] TX_EN MII PHY TX_CLK TXD[3:0] TX_EN TXCLK_10M 10M PHY
  88. 88. ARM S3C4510B 88TXD[3:0] 44,43, O TXD[3:0]LOOP_10M 40,39 TXD_10M 10M PHYTXD_10M LOOP_10MTX_EN/ 47 OTXEN_10MTX_ERR/ 45 OPCOMP_10MCRS/CRS_10M 28 IRX_CLK/ 37 I RX_CLKRXCLK_10M 25MHz 100M 2.5MHz 10M RXCLK_10M 10M PHYRXD[3:0] 35 34 IRXD_10M 33 30RX_DV/ 29 ILINK10MRX_ERR 36 ITXDA 9 ORXDA 7 InDTRA 6 O nDTRAnRTSA 8 OnCTSA 10 InDCDA 13 InSYNCA 15 ORXCA 14 ITXCA 16 I/OTXDB 20 ORXDB 18 InDTRB 17 OnRTSB 19 OnCTSB 23 InDCDB 24 InSYNCB 26 ORXCB 25 ITXCB 27 I/OUCLK 64 I UART UARTUARXD0 202 IUATXD0 204 O
  89. 89. ARM S3C4510B 89nUADTR0 203 I S3C4510BnUADSR0 205 O UART0UARXD1 206 IUATXD1 4 OnUADTR1 3 I nUADTR0nUADSR1 5 O nUADSR0P[7:0] 185-179, I/O 176XINTREQ 191-189, I/O[3:0] 186P[11:8]NXDREQ[1:0]/P[1 193,192 I/O3:12]nXDACK[1:0]/P[1 195,194 I/O5:14]TOUT0/P[16] 196 I/OTOUT1/P[17] 199 I/OSCL 200 I/OSDA 201 I/OVDDP 1 21 Power 41 56 78 92 105 118 130 155 167 177 197VDDI 11 31 Power 51 65 103 142 157 187 207VSSP 2 22 GND 42 57 79 81 93 106 119
  90. 90. ARM S3C4510B 90 131 156 168 178 198VSSI 12 32 GND 52 66 104 143 158 188 208VDDA 53 PowerVSSA 54 GND5.2.3 CPU Special Function Registers S3C4510B CPU ARM 32 ARM7TDMI5.4 ARM7TDMI RISC Reduced Instruction SetComputer CISC Complex Instruction Set Computer RISC ARM7TDMI ARM7Thumb ARM 36 32 ARM 16 Thumb ARMThumb 16 32 ARM ARM 32 ARM 16 Thumb Thumb 16 32 ARM7TDMI 32 ARM 16 Thumb Thumb ARM ARM Thumb
  91. 91. ARM S3C4510B 91
  92. 92. ARM S3C4510B 92
  93. 93. ARM S3C4510B 93 Reset 1 Data Abort 2FIQ FIQ 3IRQ IRQ 4 Prefetch Abort 5 Undefined Instruction 6SWI 6 R/W SYSCFG 0x0000 / 0x67FFFF91 CLKCON 0x3000 / 0x00000000 EXTACON0 0x3008 / I/O 1 0x00000000 EXTACON1 0x300C / I/O 2 0x00000000 EXTDBWTH 0x3010 / 0x00000000 ROMCON0 0x3014 / ROM/ARAM/FLASH 0 0x20000060 ROMCON1 0x3018 / ROM/ARAM/FLASH 1 0x00000060 ROMCON2 0x301C / ROM/ARAM/FLASH 2 0x00000060 ROMCON3 0x3020 / ROM/ARAM/FLASH 3 0x00000060 ROMCON4 0x3024 / ROM/ARAM/FLASH 4 0x00000060 ROMCON5 0x3028 / ROM/ARAM/FLASH 5 0x00000060 DRAMCON0 0x302C / DRAM 0 0x00000000 DRAMCON1 0x3030 / DRAM 1 0x00000000 DRAMCON2 0x3034 / DRAM 2 0x00000000 DRAMCON3 0x3038 / DRAM 3 0x00000000
  94. 94. ARM S3C4510B 94 REFEXTCON 0x303C / I/O 0x000083FD BDMATXCON 0x9000 / BDMA 0x00000000 BDMARXCON 0x9004 / BDMA 0x00000000(BDMA) BDMATXPTR 0x9008 / 0x00000000 BDMARXPTR 0x900C / 0x00000000 BDMARXLSZ 0x9010 / BDMASTAT 0x9014 / BDMA 0x00000000 CAM 0x9100- CAM 32 0x917C BDMATXBUF 0x9200- / BDMA Tx 0x92FC (64 ) BDMARXBUF 0x9800- / BDMA Rx 0x99FC (64 ) MACON 0xA000 / MAC 0x00000000 CAMCON 0xA004 / CAM 0x00000000(MAC) MACTXCON 0xA008 / MAC 0x00000000 MACTXSTAT 0xA00C / MAC 0x00000000 MADRXCON 0xA010 / MAC 0x00000000 MACRXSTAT 0xA014 / MAC 0x00000000 STADATA 0xA018 / 0x00000000 STACON 0xA01C / 0x00006000 CAMEN 0xA028 / CAM 0x00000000 EMISSCNT 0xA03C / 0x00000000 EPZCNT 0xA040 0x00000000 ERMPZCNT 0xA044 0x00000000 ETXSTAT 0x9040 0x00000000HDLC HMODE 0x7000 / HDLC 0x00000000A HCON 0x7004 / HDLC 0x00000000 HSTAT 0x7008 / HDLC 0x00010400 HINTEN 0x700C / HDLC 0x00000000 HTXFIFOC 0x7010 / TxFIFO _ HTXFIFOT 0x7014 TxFIFO _ HRXFIFO 0x7018 HDLC RxFIFO 0x00000000 HBRGTC 0x701C HDLC 0x00000000 HPRMB 0x7020 / HDLC 0x00000000 HSAR0 0x7024 / HDLC 0 0x00000000 HSAR1 0x7028 / HDLC 1 0x00000000
  95. 95. ARM S3C4510B 95 HSAR2 0x702C / HDLC 2 0x00000000 HSAR3 0x7030 / HDLC 3 0x00000000 HMASK 0x7034 / HDLC 0x00000000 DMATxPTR 0x7038 / DMA Tx 0xFFFFFFFF DMARxPTR 0x703C / DMA Rx 0xFFFFFFFF HMFLR 0x7040 / 0xXXXX000 HRBSR 0x7044 / DMA 0xXXXX000 0HDLC HMODE 0x8000 / HDLC 0x00000000B HCON 0x8004 / HDLC 0x00000000 HSTAT 0x8008 / HDLC 0x00010400 HINTEN 0x800C / HDLC 0x00000000 HTXFIFCO 0x8010 TxFIFO _ HTXFIFOT 0x8014 TxFIFO _ HRXFIFO 0x8018 HDLC RxFIFO 0x00000000 HBRGTC 0x801C / HDLC 0x00000000 HPRMB 0x8020 / HDLC 0x00000000 HSAR0 0x8024 / HDLC 0 0x00006000 HSAR1 0x8028 / HDLC 1 0x00000000 HSAR2 0x802C / HDLC 2 0x00000000 HSAR3 0x8030 HDLC 3 0x00000000 HMASK 0x8034 HDLC 0x00000000 DMATxPTR 0x8038 DMA Tx 0xFFFFFFFF DMARxPTR 0x803C / DMA Rx 0xFFFFFFFF HMFLR 0x8040 / 0xXXXX000 0 HRBSR 0x8044 / DMA 0xXXXX000 0I/O IOPMOD 0x5000 / I/O 0x00000000 IOPCON 0x5004 / I/O 0x00000000 IOPDATA 0x5008 / I/O INTMOD 0x4000 / 0x00000000 INTPND 0x4004 / 0x00000000 INTMSK 0x4008 / 0x003FFFFF INTPRI0 0x400C / 0 0x03020100 INTPRI1 0x4010 / 1 0x07060504
  96. 96. ARM S3C4510B 96 INTPRI2 0x4014 / 2 0x0B0A0908 INTPRI3 0x4018 / 3 0x0F0E0D0C INTPRI4 0x401C / 4 0x13121110 INTPRI5 0x4020 / 5 0x00000014 INTOFFSET 0x4024 0x00000054 INTOSET_FIQ 0x4030 FIQ 0x00000054 INTOSET_IRQ 0x4034 IRQ 0x00000054IIC IICCON 0XF000 / IIC 0x00000054 IICBUF 0xF004 / IIC IICPS 0xF008 / IIC 0x00000000 IICCONOUT 0xF00C IIC 0x00000000GDMA GDMACON0 0xB000 / GDMA 0 0x00000000 GDMACON1 0xC000 / GDMA 1 0x00000000 GDMASRC0 0xB004 / GDMA 0 GDMADST0 0xB008 / GDMA 0 GDMASRC1 0xC004 / GDMA 1 GDMADST1 0xB008 / GDMA 1 GDMACNT0 0xB00C / GDMA 0 GDAMCNT1 0xC00C / GDMA 1UART ULCON0 0xD000 / UART 0 0x00 ULCON1 0xE000 / UART 1 0x00 UCON0 0xD004 / UART 0 0x00 UCON1 0xE004 / UART 1 0x00 USTAT0 0xD008 UART 0 0xC0 USTAT1 0xE008 UART 1 0xC0 UTXBUF0 0xD00C UART 0 UTXBUF1 0xE00C UART 1 URXBUF0 0xD010 UART 0 URXBUF1 0xE010 UART 1 UBRDIV0 0xD014 / 0 0x00 UBRDIV1 0xE014 / 1 0x00 TMOD 0x6000 / 0x00000000 TDATA0 0x6004 / 0 0x00000000 TDATA1 0x6008 / 1 0x00000000 TCNT0 0x600C / 0 0xFFFFFFFF TCNT1 0x6010 / 1 0xFFFFFFFF
  97. 97. ARM S3C4510B 975.2.4 S3C4510B1. S3C4510B System Manager 8 16 S3C4510B S3C4510B — — DMA CPU DRAM DRAM normal/EDO SDRAM SYSCFG[31] normal/EDO SDRAM — S3C4510B ROM/SRAM I/O — — I/O S3C4510B S3C4510B S3C4510B nEWAIT nEWAIT CPU2. (System Manager Registers) / — — — RAS CAS — — ARM 4GB Flash SRAM SDRAM Memory Bank 5.5 S3C4510BROM/SRAM/Flash DRAM I/O Base Pointer 64KB 16 26 10 S3C4510B 2 64MB 16M
  98. 98. ARM S3C4510B 98 5.5S3C4510B S3C4510B S3C4510B I/O 64MB 5.5 Base Pointer End Pointer
  99. 99. ARM S3C4510B 99 I/O I/O 0 I/O 1 I/O 0 +16KB I/O2 I/O 0 +32KB I/O 3I/O 0 +48KB I/O 0 +64KB I/O 64KB 16 , “ 16 - 1” ROM/SRAM/Flash 0ROM/SRAM/Flash 0 ROM/SRAM/Flash 0 0x200 0x0 ROM/SRAM/Flash 0 32MB0x0000,0000 0x0200,0000-1 ROM/SRAM/Flash 0ROM ROM/SRAM/Flash 0 0x3FF0000 5.6
  100. 100. ARM S3C4510B 100 5-4SYSCFG 0x0000 / 0x67FFFF91CLKCON 0x3000 / 0x00000000EXTACON0 0x3008 / I/O 1 0x00000000EXTACON1 0x300C / I/O 2 0x00000000EXTDBWTH 0x3010 / 0x00000000ROMCON0 0x3014 / ROM/ARAM/Flash 0 0x20000060ROMCON1 0x3018 / ROM/ARAM/Flash 1 0x00000060ROMCON2 0x301C / ROM/ARAM/Flash 2 0x00000060ROMCON3 0x3020 / ROM/ARAM/Flash 3 0x00000060ROMCON4 0x3024 / ROM/ARAM/Flash 4 0x00000060ROMCON5 0x3028 / ROM/ARAM/Flash 5 0x00000060DRAMCON0 0x302C / DRAM 0 0x00000000DRAMCON1 0x3030 / DRAM 1 0x00000000DRAMCON2 0x3034 / DRAM 2 0x00000000DRAMCON3 0x3038 / DRAM 3 0x00000000REFEXTCON 0x303C / I/O 0x000083FD ARM S3C4510BARM7TDMI 32 4GB 2 A[1:0] A[0] ARM S3C4510B S3C4510BS3C4510B A[0] A[0] 5.6 5-5 ADDR[21:0]
  101. 101. ARM S3C4510B 1018 A21-A0 4M16 A22-A1 4M32 A23-A2 4M S3C4510BS3C4510B S3C4510B S3C4510B 5-6 A-1 ADRAM A-2General DMA1 GDMA1 A-3General DMA0 GDMA0 A-4 B HDLC B A-5 A HDLC A A-6MAC DMA BDMA A-7 A B-1 B B-2 B
  102. 102. ARM S3C4510B 102 S3C4510B A B S3C4510B ExtMREQs CPU ExtMACK S3C4510B S3C4510B DRAM DRAM3. Control Register SYSCFG SRAM 64KB 5.5 SYSCFG DRAMSRAM SYSCFG SYSCFG 0x0000 / 0x67FFFF91 0 1 Cache 1 8KB Cache SRAM 00 = 4KB SRAM 4KB Cache 01 = 0KB SRAM 8KB Cache 10 = 8KB SRAM 0KB Cache 10 CE
  103. 103. ARM S3C4510B 103 16 SRAM 16 00001=S3C4510X KS32C50100 11001=S3C4510B 0 4 DRAM /EDO DRAM 1 4 DRAM SDRAM0x3FF0000 SYSCFG 64MB 0x3FF0000 ROMCON 0x3014 ROMCON 0x3FF0000 0x3014 0x3FF3014 0x3000000 ROMCON 0x3003014 0x3FF0000 SYSCFG CE Cache Cache Cache 8KB SRAM SYSCFG[5 4] Cache 8KB Cache SRAM SRAM S3C4510B 4 CPU 4 ARM7TDMI4. MUX (System clock and MUX Bus Control Register)
  104. 104. ARM S3C4510B 104 EXTDBWTHEXTDBWTH 0x3010 / 0x00000000
  105. 105. ARM S3C4510B 105 ROM/SRAM/FlashROMCON0 0x3014 / ROM/SRAM/Flash 0 0x20000060ROMCON1 0x3018 / ROM/SRAM/Flash 1 0x00000060ROMCON2 0x301C / ROM/SRAM/Flash 2 0x00000060ROMCON3 0x3020 / ROM/SRAM/Flash 3 0x00000060ROMCON4 0x3024 / ROM/SRAM/Flash 4 0x00000060
  106. 106. ARM S3C4510B 106ROMCON5 0x3028 / ROM/SRAM/Flash 5 0x00000060 DRAM I/ODRAMCON0 0x302C / DRAM 0 0x00000000DRAMCON1 0x3030 / DRAM 1 0x00000000DRAMCON2 0x3034 / DRAM 2 0x00000000DRAMCON3 0x3038 / DRAM 3 0x00000000REFEXTCON 0x303C / I/O 0x00000000
  107. 107. ARM S3C4510B 107————
  108. 108. ARM S3C4510B 108 4 DRAM 0x00000000DRAM
  109. 109. ARM S3C4510B 109 S3C4510B S3C4510B5.35.3.1 S3C4510B S3C4510B 208 QFP 8 /16 DIP S3C4510B 50 I/O HDLCUART IIC MAC S3C4510B I O / I/O S3C4510B S3C4510B S3C4510B / S3C4510B S3C4510B S3C4510B = = PLL 820pF PLL
  110. 110. ARM S3C4510B 110 IEEE TCK TMS TDI nTRST S3C4510B JTAG ARM = = ’01’ = 8 ’10’ = 16 ’11’ =32 ’00’ = = = SDRAM CPU = XCLK =XCLK PLL S3C4510B / CPU5.3.2 5V 3.3V S3C4510B 3.3V 5V 5V 5.8
  111. 111. ARM S3C4510B 111 DC-DC 5V 3.3V Linear Technology LT108X LT1083 7.5A LT1084 5A LT1085 3A LT1086 1.5A5.3.3 CPU S3C4510B 5.9 S3C4510B PLL 10MHz10MHz S3C4510B PLL 50MHz PLL 1 5V 3.3V 2 3 4 22 S3C4510B XCLK RC RC 5.10
  112. 112. ARM S3C4510B 112 R1 C1 C1 nReset C1 nReset S1 C1 nReset Reset nReset R1 C15.3.4 Flash Flash In-System Flash Flash 8 16 3.3V ATMEL AMD HYUNDAI Flash HY29LV160 Flash
  113. 113. ARM S3C4510B 113 HY29LV160 16M 2M 2.7V 3.6V48 TSOP 48 FBGA 16 8 16 HY29LV160 3V Flash HY29LV160 5.11 5.12 5-11
  114. 114. ARM S3C4510B 114 5-11 HY29LV160A[19:0] IDQ[15]/A[-1] I/O 8 16DQ[14:0] DQ[15]/A[-1] 21 DQ[14:8]BYTE# ICE# IOE# IWE# IRESET# IRY/BY# OVCC -- 3.3VVSS --

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