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ScalableCore system at SACSIS2010, NARA

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ScalableCoreシステム 1.1 @SACSIS2010, 奈良

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ScalableCore system at SACSIS2010, NARA

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  7. 7.         Off chip main memory Off chip main memory Mem. Node Page (0,0) buffer Y- Many-core processor chip INCC Memory Path Path Path Comp. Node Node Node Node Node (X,Y) Core (0,0) (1,0) (2,0) (M,0) Router X+ Path Comp. Comp. Comp. Node INCC Node Node Node Node Memory (0,1) (1,1) (2,1) (M,1) (b) Y+ X- Router X+ Path Comp. Comp. Comp. Y- Node Node Node Node (0,2) (1,2) (2,2) (M,2) Path Node (a) Y+ (X,Y) Path Comp. Comp. Comp. Node Node Node Node X- Router X+ (0,N) (1,N) (2,N) (M,N) (c) Y+
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  9. 9.   1600 SimMc Simulation Speed (kilo cycle / sec) 1400 1200 1000 800 600 400 200 0 20 40 60 80 100 # nodes
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  26. 26.         809' 6:5451' 6<5451' #+.' %?@ABC!7* !"##$%&'()* !"##$%D.0-'* /425 &+,-'. 6>5451' /'.0(1$/'2)023 ;5451' ==5451' 6$70.-,(1$#451'
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  30. 30.             •  •    • 
  31. 31.   Simulation Speed (kilo virtual cycle / sec) 1600 Speedup SimMc 1400 ScalableCore system 20 1200 1000 15 Speedup 800 10 600 400 5 200 0 0 20 40 60 80 100 # nodes
  32. 32.   2 Relative Efficiency 1.8 SimMc 30 ScalableCore system 1.6 Energy [J/virtual cycle] 25 Relative Efficiency 1.4 1.2 20 1 15 0.8 0.6 10 0.4 5 0.2 0 0 20 40 60 80 100 # nodes
  33. 33.   Energy-Delay Product [J sec/virtual cycle] 0.045 600 Relative Efficiency 0.04 SimMc ScalableCore system 500 0.035 Relative Efficiency 0.03 400 0.025 300 0.02 0.015 200 0.01 100 0.005 0 0 20 40 60 80 100 # nodes
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