2010-01-18 リコンフィギュラブルシステム研究会@慶応大学日吉

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3. Intel Single Chip Cloud Computer
48 cores (x86)
TILERA TILE-Gx100
100 cores (MIPS)

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Off chip main memory
Off chip main memory
Mem. Node Page
(0,0) buffer Y-
Many-core processor chip
INCC
Memory Path Path Path Comp. Node
Node Node Node Node (X,Y) Core
(0,0) (1,0) (2,0) (M,0)
Router X+ Path Comp. Comp. Comp. Node INCC
Node Node Node Node Memory
(0,1) (1,1) (2,1) (M,1)
(b) Y+
X- Router X+
Path Comp. Comp. Comp.
Y- Node Node Node Node
(0,2) (1,2) (2,2) (M,2)
Path Node (a) Y+
(X,Y)
Path Comp. Comp. Comp.
Node Node Node Node
X- Router X+ (0,N) (1,N) (2,N) (M,N)
(c) Y+

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Reality
Difficulty to construct

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Off chip main memory
Off chip main memory
Mem. Node Page
(0,0) buffer Y-
Many-core processor chip
INCC Memory Path Path Path Comp. Node
Node Node Node Node (X,Y) Core
(0,0) (1,0) (2,0) (M,0)
Router X+ Path Comp. Comp. Comp. Node INCC
Node Node Node Node Memory
(0,1) (1,1) (2,1) (M,1)
(b) Y+
X- Router X+
Path Comp. Comp. Comp.
Y- Node Node Node Node
(0,2) (1,2) (2,2) (M,2)
Path Node (a) Y+
(X,Y)
Path Comp. Comp. Comp.
Node Node Node Node
X- Router X+ (0,N) (1,N) (2,N) (M,N)
(c) Y+

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15. volatile static int start_flag = 0;
n volatile int end_flag [RANKY_MAX][RANKX_MAX];
void send_startflag(int rank) {
int rank_x, rank_y;
rank_x = getidx(rank);
l rank_y = getidy(rank);
int dst,x,y;
for(y=1;y<=max_rank_y;y++){
for(x=1;x<=max_rank_x;x++){
end_flag[y-1][x-1] = 0;
l }
}
for(x=1;x<=rank_x;x++){
for(y=1;y<=rank_y;y++){
if(x==1 && y==1) continue;
setidxy(&dst, x, y);
MC_dma_put_4b(dst, (int *)&start_flag, 1);
}
}
}
void wait_startflag() {
while(!start_flag);
}

16. Node Node Node Node
(0,1) (1,1) (2,1) (3,1)
Node Node Node Node
(0,2) (1,2) (2,2) (3,2)
Node Node Node Node
(0,3) (1,3) (2,3) (3,3)

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time
Node 0 0 1 2 3 4 5 6 7 8 9 10 11
Node 1 0 1 2 3 4 5 6 7 8 9 10 11
Node 2 0 1 2 3 4 5 6 7 8 9 10 11

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