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# Writing more complex models

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Modeling more complicated logic using sequential statements
Skills gained:
1- Identify sequential environment in VHDL
2- Model simple sequential logic

This is part of VHDL 360 course

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### Writing more complex models

3. 3. Objective<br />Modeling more complicated logic using sequential statements<br />Skills gained:<br />Identify sequential environment in VHDL<br />Model simple sequential logic<br />VHDL 360 ©<br />3<br />
4. 4. Outline<br />Process Description <br />Data Objects<br />Sequential Statements<br />Case Statement<br />IF Statement<br />VHDL 360 ©<br />4<br />
5. 5. Statements<br />VHDL has concurrent statements and sequential statements<br />Concurrent statements are executed in parallel with respect to each other, we explained some of them in Module 1*<br />Sequential statements are executed in sequence with respect to each other.<br />Sequential statements should be written inside a “process”<br />VHDL 360 ©<br />5<br />Module 1: Create your first model for a simple logic circuit<br />
6. 6. Process Description<br />Process ( <sensitivity_list> )<br />-- process declarations <br />begin<br />-- process body<br />endprocess;<br />6<br />VHDL 360 ©<br />Syntax:<br />Process declarations: defines variables, subprograms…etc to be used in process body<br />Process body: defines implementation details of input/output relationship in a sequential manner<br /><sensitivity_list>: List of signals/ports that cause the process to be executed whenever there is a change in their values<br />Example 1:<br />Architecture behave of example1 is<br />Begin<br /> process(x,y)-- Every time "x" or "y" value is changed, the process will be executed<br /> begin<br />myOutput<= x nand y;<br /> endprocess;<br />End behave ;<br />
7. 7. Sequential Assignments<br />Statements inside a “process” are read sequentially and executed when the “process” suspends<br />Signal assignment statement like “F <= A” causes a transaction to be scheduled<br />This means; the current value of A is read and scheduled to drive F when the process suspends.<br />“Process” suspends in two situations<br />When “end process” is reached<br />When a “wait” statement is reached<br />7<br />VHDL 360 ©<br />Example 2:<br />process(...)-- Assume that initially A = '1' while G, F, Z and X = 'U' <br />Begin<br /> Z <= A;-- Signal assignment, schedule a change/transaction,<br /> -- however the value of Z still equals 'U'<br /> G <='1';<br /> F <= G;-- G is not yet updated, so F is assigned the old value of G<br /> X <= F;-- Similarly, X is assigned the old value of F<br /> G <='0';-- overrides the previous scheduled transaction,<br /> -- however the value of G still equals 'U' <br /> Z <= G;<br />endprocess;-- Process suspends => Signals update with scheduled transactions<br /> -- G = '0', F = 'U', Z = 'U', X = 'U'<br />
8. 8. Sequential Assignments<br />8<br />VHDL 360 ©<br />Example 3:<br />Architecture behave offulladderis<br /> signal temp :std_logic;<br />Begin<br />process(In1, In2, CarryIn)<br />begin<br />temp <= In1 XOR In2;<br /> Sum <= temp XORCarryIn;<br />CarryOut<= (In1 AND In2) OR (CarryInAND temp);<br />endprocess;<br />End behave ;<br />There’s a problem here!<br />
9. 9. Data Objects<br />9<br />VHDL 360 ©<br />VHDL offers different data objects:<br />Constants<br />Used to store values that can’t be changed during simulation time <br />Signals<br />Used to model connections<br />Signals can be <br />External (Ports) used as an interface for the entity to the outside world (Declared in Entity)<br />Internal used inside the architecture to connect different logic parts (Usually declared in architecture)<br />Assigned using “<=”<br />Outside a process, its value is updated when their signal assignment is executed.<br />Inside a process, its value is updated after the process suspends<br />Variables<br />Used for computations<br />Variables are declared inside a process or sub-programs<br />Assigned using “:=”<br />Value is updated immediately<br />Constant Declaration<br />constant <con_name>: <con_type>;<br />Signal Declaration<br />signal <sig_name>: <sig_type>;<br />Variable Declaration<br />variable <var_name>: <var_type>;<br />
10. 10. Objects Scope<br />10<br />VHDL 360 ©<br />Each object in VHDL has a scope following the below rules:<br />Objects declared in package are available to all units using that package<br />Objects declared in an entity are available to all architectures of that entity<br />Objects declared in an architecture are available to all statements in that architecture<br />Objects declared in a process are available only within that process<br />Entity<br />architecture1<br />architecture2<br />process1<br />architecture3<br />process2<br />
11. 11. Data Objects Example<br />11<br />VHDL 360 ©<br />architecturebehavofmydutis<br />-- Signals scope is the whole architecture<br />signal x, y :std_logic:= 'U';-- Initialization (Not an assignment)<br />signalsigbus:std_logic_vector(7downto0):="01011110"; <br />begin<br /> process()-- No sensitivity list, Is this a problem?<br />-- Variables are declared inside a process<br /> -- Variables scope is limited to the process<br />variable z :std_logic:= '1';<br />variablevarbus:std_logic_vector(3downto0):="0001";<br />begin<br /> x <= '1';-- Signal assignment, schedule a change, <br /> -- however the value of x still equals 'U'<br />sigbus<="00110101";<br /> z := '1';-- Variable assignment takes effect immediately<br />varbus:="1101";<br />sigbus(3downto0)<=varbusand"1010";-- overrides the previous scheduled change,<br /> -- however sigbus still equals "01011110"<br /> x <= z and '0';<br /> z := '0';<br /> y <= z xor '0';<br />endprocess;-- Process suspends => x = '0', y = '0' and sigbus = "00111000"<br />endarchitecture;<br />
12. 12. Skills Check<br />12<br />VHDL 360 ©<br /><ul><li>Complete the below table with the values of var1, temp & q when the below code is executed where each column represents a new value of a & b</li></ul>process(a,b)<br />variablevar1: integer;<br />begin<br />var1:=a+b;<br />temp<=var1;<br />q<=temp;<br />endprocess;<br />Golden rules of thumb<br /><ul><li>Variables are updated immediately
13. 13. Signals are updated after the process suspends</li></li></ul><li>Skills Check (Soln.)<br />13<br />VHDL 360 ©<br /><ul><li>Complete the below table with the values of var1, temp & q when the below code is executed where each column represents a new value of a & b</li></ul>process(a,b)<br />variablevar1: integer;<br />begin<br />var1:=a+b;<br />temp<=var1;<br />q<=temp;<br />endprocess;<br />Golden rules of thumb<br /><ul><li>Variables are updated immediately
14. 14. Signals are updated after the process suspends</li></li></ul><li>Skills Check (Soln.)<br />14<br />VHDL 360 ©<br /><ul><li>Complete the below table with the values of var1, temp & q when the below code is executed where each column represents a new value of a & b</li></ul>process(a,b)<br />variablevar1: integer;<br />begin<br />var1:=a+b;<br />temp<=var1;<br />q<=temp;<br />endprocess;<br />Golden rules of thumb<br /><ul><li>Variables are updated immediately
15. 15. Signals are updated after the process suspends</li></li></ul><li>Skills Check<br />15<br />VHDL 360 ©<br />One of the below examples has an error, find the error <br />
16. 16. Sequential Statements<br />Now let’s introduce sequential statements<br />Case statement<br />If statement<br />loop statements <br />Wait statement<br />Think Hardware<br />VHDL 360 ©<br />16<br />
17. 17. 17<br />VHDL 360 ©<br />a<br />b<br />F<br />c<br />d<br />Sel(1:0)<br />Case Statement<br /><ul><li>Makes several conditions on the same signal</li></ul><expression> can be a signal or a variable<br /><choice> constants representing one of possible <expression> values.<br />“When others” is a must if not all values of <expression> are covered<br />Each branch of a Case statement can have any number of sequential statements<br />Syntax:<br />case <expression> is <br />when <choice> => <br /> -- list of sequential statements<br />when <choice> => <br /> -- list of sequential statements<br />when others => <br />-- list of sequential statements<br /> end case;<br />Example 4:<br />Architecturertlofmux_caseis<br />begin<br /> process(a,b,c,d,sel)isbegin<br />Caseselis<br /> When"00"=><br /> f <= a;<br /> When"01"=><br /> f <= b;<br /> When"10"=><br /> f <= c;<br /> When"11"=><br /> f <= d;<br /> whenothers=>-- is "when others" a must?<br /> f <= a;<br />Endcase;<br /> Endprocess;<br />Endarchitecture;<br />
18. 18. 18<br />VHDL 360 ©<br />a<br />b<br />F<br />c<br />d<br />Sel(1:0)<br />Case Statement<br /><ul><li>Makes several conditions on the same signal</li></ul><expression> can be a signal or a variable<br /><choice> constants representing one of possible <expression> values.<br />“When others” is a must if not all values of <expression> are covered<br />Each branch of a Case statement can have any number of sequential statements<br />Syntax:<br />case <expression> is <br />when <choice> => <br /> -- list of sequential statements<br />when <choice> => <br /> -- list of sequential statements<br />when others => <br />-- list of sequential statements<br /> end case;<br />Example 4:<br />Architecturertlofmux_caseis<br />begin<br /> process(a,b,c,d,sel)isbegin<br />Caseselis<br /> When"00"=><br /> f <= a;<br /> When"01"=><br /> f <= b;<br /> When"10"=><br /> f <= c;<br /> When"11"=><br /> f <= d;<br /> whenothers=><br /> f <= a;<br />Endcase;<br /> Endprocess;<br />Endarchitecture;<br />Do we need all these signals?<br />
19. 19. Exercise 1 <br />19<br />VHDL 360 ©<br />a<br />F<br />2<br />4<br />The below code is 2x4 Decoder; Complete it by doing the following:<br />Declare F as an output port<br />Add necessary signals to sensitivity list<br />Add Case statement with all needed branches to create a 2x4 decoder<br />libraryIEEE;<br />useIEEE.std_logic_1164.all;<br />entity decoder2x4 is<br /> port(a:instd_logic_vector(1downto0);<br />-- Declare F as an output port<br /><here><br />);<br />endentity;<br />Architecture behave of decoder2x4 is<br />Begin<br />process(<here>)-- Add necessary signals to sensitivity list<br />begin<br />-- Add Case statement with all needed branches to create a 2x4 decoder<br /><here><br />endprocess;<br />EndArchitecture;<br />
20. 20. Sequential Statements<br />Sequential Statements<br />Case statement <br />If statement<br />loop statements <br />Wait statement<br />Think Hardware<br />VHDL 360 ©<br />20<br />
21. 21. IF Statement<br />If <condition> then <br />-- list of sequential statements<br />elsif<condition>then<br /> -- list of sequential statements<br />…<br />else<br />-- list of sequential statements<br />end if;<br />21<br />VHDL 360 ©<br /><ul><li>Executes a list of sequential statements when the corresponding condition evaluates to true</li></ul><condition> Boolean expression that evaluates to either TRUE or FALSE<br />The branches order is important as they imply a priority <br />Syntax:<br />Example 5:<br />Libraryieee;<br />useieee.std_logic_1164.all;<br />Entityd_ffis<br />Port( d,clk,rst:instd_logic;<br /> Q,nQ:outstd_logic);<br />endentity;<br />Architecturebehavofd_ffis<br />signalQ_int:std_logic;<br />Begin<br />process(clk,rst)<br />begin<br />If(rst= '1')then<br />Q_int<= '0';<br />elsifrising_edge(clk)then<br />Q_int<= d;<br /> endif;<br />endprocess;<br />Q <=Q_int;<br />nQ<=not (Q_int);<br />endbehav;<br />Since rst has higher priority over the clk edge<br /><br />D Flip Flop with asynchronous reset<br />rising_edge() : defined for std_logic type<br />
22. 22. Exercise 2 <br />The below code is D Flip-flop with synchronous reset; Complete it by doing the following:<br />Add necessary signals to sensitivity list<br />Add necessary condition to model the rising edge of the clock<br />Add nested If statement to model the synchronous reset<br />22<br />VHDL 360 ©<br />Libraryieee;<br />useieee.std_logic_1164.all;<br />Entityd_ffis<br />Port( d,clk,rst:instd_logic;<br /> Q,nQ:outstd_logic);<br />endentity;<br />Architecturebehavofd_ffis<br />signalQ_int:std_logic;<br />Begin<br />process(...) -- Add necessary signals to sensitivity list<br />begin<br />If(...)then-- Add necessary condition for a rising edge clock<br /> ...<br />-- Add a nested If statement to model the synchronous reset<br /> endif;<br />endprocess;<br />Q <=Q_int;<br />nQ<=not (Q_int);<br />endbehav;<br />
23. 23. IF Statement<br />23<br />VHDL 360 ©<br />Example 6:<br />LIBRARYieee;<br />USEieee.std_logic_1164.all;<br />USEieee.std_logic_arith.all;<br />ENTITYadd_subIS<br />port(a, b :ininteger;<br /> result :outinteger;<br />operation:instd_logic);-- add or subtract<br />ENDENTITYadd_sub;<br />ARCHITECTURE behave OFadd_subIS<br />BEGIN<br />process(a, b, operation)<br />begin<br />if(operation = '1')then -- Add when operation = '1'<br />result <= a + b;<br />else-- Subtract otherwise<br /> result <= a - b;<br />endif;<br />endprocess;<br />ENDARCHITECTURE behave;<br />
24. 24. Exercise 3 <br />The below code is a simple comparator; Complete it by doing the following:<br />Declare 2 bits output port called “result”<br />Add necessary conditions to model “equal to” and “greater than” Comparisons<br />Add another “elsif” branch for “smaller than” comparison<br />24<br />VHDL 360 ©<br />LIBRARYieee;<br />USEieee.std_logic_1164.all;<br />USEieee.std_logic_unsigned.all;<br />ENTITY comparator IS<br /> port(a, b:instd_logic_vector(7downto0);<br /> -- Declare a 2 bits output port called "result“<br /> );<br />ENDENTITY;<br />ARCHITECTURE behave OF comparator IS<br />BEGIN<br /> process(a, b)<br /> begin<br /> if(...)then-- equality <br /> result <="00";<br />elsif(...)then-- greater than <br /> result <="01";<br /> ...-- Add another "elsif" branch for "smaller than" comparison<br /> else-- covers other cases <br /> result <="11";<br /> endif;<br /> endprocess;<br />ENDARCHITECTURE;<br />