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# Synthesis Examples

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Getting familiar with code changes' impact on synthesis
Skills gained:
1- Writing synthesis friendly code

This is part of VHDL 360 course

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### Synthesis Examples

3. 3. Module 4<br />Synthesis Examples<br />
4. 4. Objective<br />Getting familiar with code changes' impact on synthesis<br />Skills gained:<br />Writing synthesis friendly code<br />VHDL 360 ©<br />4<br />
5. 5. Outline<br />Introduction<br />Synthesize and Learn<br />Combinational Logic<br />Latch Inference<br />Sequential Logic<br />Flip-Flop Inference<br />VHDL 360 ©<br />5<br />
6. 6. Introduction<br />VHDL 360 ©<br />6<br />VHDL is a H/W modeling language used to model digital circuits<br />Digital circuits can be either Combinational or Sequential<br />Combinational Logic circuits: Implement Boolean functions whose output is only dependant on the present inputs<br />Sequential Logic circuits: Implement circuits whose output depends on the present inputs & the history of the inputs. i.e. Circuits having storage elements<br />
7. 7. Introduction<br />VHDL 360 ©<br />7<br />VHDL Standard<br />Synthesizable VHDL<br />Synthesis tools translate the VHDL code to a gate level netlist representing the actual H/W gates [and, or, not, Flip-Flops…etc]<br />Only a subset of the language is synthesizable<br />A model can be either<br />Synthesizable: Used for both Simulation & Synthesis<br />Non-Synthesizable: Used for Simulation only<br />
8. 8. Synthesize And Learn<br />8<br />
9. 9. Synthesize and Learn<br />In the next slides we will use examples from the previous modules to demonstrate synthesis and study the synthesized logic<br />We will also modify these examples and observe the impact on the synthesized logic<br />9<br />VHDL 360 ©<br />
10. 10. Combinational Logic<br />libraryIEEE;<br />useIEEE.std_logic_1164.all;<br />Entitymux_caseis<br /> Port(a, b, c, d:instd_logic;<br />Sel:instd_logic_vector(1downto0);<br /> F:outstd_logic);<br />Endentity;<br />Architecture rtl ofmux_caseis<br />begin<br /> process(a,b,c,d,sel)is<br />begin<br />Caseselis<br />When"00"=> f <= a;<br />When"01"=> f <= b;<br />When"10"=> f <= c;<br />When"11"=> f <= d;<br />whenothers=> f <= a;<br />Endcase;<br /> Endprocess;<br />Endarchitecture;<br />VHDL 360 ©<br />10<br />Example 1: 4x1 Multiplexer<br />
11. 11. Skills Check<br /><ul><li>What is the impact of removing some signals from the sensitivity list as shown in example 2? </li></ul>Architecture rtl ofmux_caseis<br />begin<br /> process(a,b,c,d,sel)is<br />begin<br />Caseselis<br />When"00"=> f <= a;<br />When"01"=> f <= b;<br />When"10"=> f <= c;<br />When"11"=> f <= d;<br />whenothers=> f <= a;<br />Endcase;<br /> Endprocess;<br />Endarchitecture;<br />VHDL 360 ©<br />11<br />Example 1: 4x1 Multiplexer<br />Example 2: 4x1 Multiplexer <br />Architecture rtl ofmux_caseis<br />begin<br /> process(a, sel)is<br />begin<br />Caseselis<br />When"00"=> f <= a;<br />When"01"=> f <= b;<br />When"10"=> f <= c;<br />When"11"=> f <= d;<br />whenothers=> f <= a;<br />Endcase;<br /> Endprocess;<br />Endarchitecture;<br />
12. 12. Skills Check (Soln.)<br />Architecture rtl ofmux_caseis<br />begin<br /> process(a,b,c,d,sel)is<br />begin<br />Caseselis<br />When"00"=> f <= a;<br />When"01"=> f <= b;<br />When"10"=> f <= c;<br />When"11"=> f <= d;<br />whenothers=> f <= a;<br />Endcase;<br /> Endprocess;<br />Endarchitecture;<br />VHDL 360 ©<br />12<br /><ul><li>No Impact on the synthesis results, however we will find that the simulation results differ
13. 13. Synthesis tools don’t use the sensitivity list to determine the logic, but simulation tools depend on the sensitivity list to execute the process
14. 14. Example 2 suffers a problem called “Simulation – Synthesis mismatch”</li></ul>Example 1: 4x1 Multiplexer<br />Example 2: 4x1 Multiplexer<br />Architecture rtl ofmux_caseis<br />begin<br /> process(a, sel)is<br />begin<br />Caseselis<br />When"00"=> f <= a;<br />When"01"=> f <= b;<br />When"10"=> f <= c;<br />When"11"=> f <= d;<br />whenothers=> f <= a;<br />Endcase;<br /> Endprocess;<br />Endarchitecture;<br />
15. 15. Combinational Logic<br /><ul><li>VHDL 2008* introduced the keyword "all" that implicitly adds all read signals to the sensitivity list to avoid “Simulation Synthesis mismatch”</li></ul>Architecture rtl ofmux_caseis<br />begin<br /> process(all)is<br /> begin<br />Caseselis<br />When"00"=> f <= a;<br />When"01"=> f <= b;<br />When"10"=> f <= c;<br />When"11"=> f <= d;<br />whenothers=> f <= a;<br />Endcase;<br /> Endprocess;<br />Endarchitecture;<br />VHDL 360 ©<br />13<br />Example 3<br />Golden rule of thumb<br /><ul><li>To avoid “Simulation Synthesis mismatch” problems when modeling Combinational logic, add all read signals to the sensitivity list</li></ul>*Not yet supported by all tools in the market<br />
16. 16. Combinational Logic<br />14<br />VHDL 360 ©<br />Example 4: Adder-Subtractor<br />LIBRARYieee;<br />USEieee.std_logic_1164.all;<br />USEieee.std_logic_arith.all;<br />ENTITYadd_subIS<br />port(a, b :ininteger;<br /> result :outinteger;<br />operation:instd_logic);<br />ENDENTITY;<br />ARCHITECTURE behave OFadd_subIS<br />BEGIN<br />process(a, b, operation)<br />begin<br />if(operation = '1')then<br />result <= a + b;<br />else<br /> result <= a - b;<br />endif;<br />endprocess;<br />ENDARCHITECTURE;<br />
17. 17. Combinational Logic<br />15<br />VHDL 360 ©<br />Consider that someone tries to re-use that code to implement an adder with an enable  He modifies the add_sub example; removes the else branch & renames the “operation” port to “enable” as shown below, How would these changes affect the logic?<br />Example 5:<br />LIBRARYieee;<br />USEieee.std_logic_1164.all;<br />USEieee.std_logic_arith.all;<br />ENTITY adder IS<br />port(a, b :ininteger;<br /> result :outinteger;<br />enable:instd_logic);<br />ENDENTITY adder;<br />ARCHITECTURE behave OF adder IS<br />BEGIN<br />process(a, b, enable)<br />begin<br />if(enable = '1')then <br />result <= a + b;<br />endif;<br />endprocess;<br />ENDARCHITECTURE;<br />
18. 18. Combinational Logic<br />16<br />VHDL 360 ©<br />This will infer a latch, because we didn’t specify what should happen to “result” when “enable” isn’t equal to '1'<br />Simulation & synthesis tools will just keep the value as is…i.e. It latches the last value<br />Example 5:<br />LIBRARYieee;<br />USEieee.std_logic_1164.all;<br />USEieee.std_logic_arith.all;<br />ENTITY adder IS<br />port(a, b :ininteger;<br /> result :outinteger;<br />enable:instd_logic);<br />ENDENTITY adder;<br />ARCHITECTURE behave OF adder IS<br />BEGIN<br />process(a, b, enable)<br />begin<br />if(enable = '1')then <br />result <= a + b;<br />endif;<br />endprocess;<br />ENDARCHITECTURE;<br />
19. 19. Combinational Logic<br />In the below example, the "11" value of "sel" signal is not listed as a case choice, hence signal "F" is not assigned a value in this case<br />A Latch is inferred in this example  Probably that wasn’t needed<br />Example 6:<br />LIBRARYieee;<br />USEieee.std_logic_1164.all;<br />ENTITYincomplete_caseIS<br />port(sel:std_logic_vector(1downto0);<br /> A, B:std_logic;<br /> F :outstd_logic);<br />ENDENTITY;<br />ARCHITECTURE rtl OFincomplete_caseIS<br />BEGIN<br /> process(sel, A, B)<br /> begin<br /> case(sel)is<br /> when"00"=><br /> F <= A;<br /> when"01"=><br /> F <= B;<br /> when"10"=><br /> F <= A xor B;<br /> whenothers=>null;<br /> endcase;<br /> endprocess;<br />ENDARCHITECTURE;<br />17<br />VHDL 360 ©<br />
20. 20. Skills Check<br />Do you think a Latch would be inferred in the below example?<br />Example 7:<br />LIBRARYieee;<br />USEieee.std_logic_1164.all;<br />ENTITYincomplete_assignmentIS<br /> port(sel:instd_logic_vector(1downto0);<br /> A, B :instd_logic;<br /> O1, O2:outstd_logic);<br />ENDENTITY;<br />ARCHITECTURE rtl OFincomplete_assignmentIS<br />BEGIN<br /> process(sel, A, B)begin<br /> case(sel)is<br /> when"00"=><br /> O1 <= A;<br /> O2 <= A and B;<br /> when"01"=><br /> O1 <= B;<br /> O2 <= A xor B;<br /> when"10"=><br /> O1 <= A xor B;<br /> when"11"=><br /> O2 <= A or B;<br /> whenothers=><br /> O1 <= '0';<br /> O2 <= '0';<br /> endcase;<br /> endprocess;<br />ENDARCHITECTURE;<br />18<br />VHDL 360 ©<br />
21. 21. Skills Check (Soln.)<br />Example 7:<br />LIBRARYieee;<br />USEieee.std_logic_1164.all;<br />ENTITYincomplete_assignmentIS<br /> port(sel:instd_logic_vector(1downto0);<br /> A, B :instd_logic;<br /> O1, O2:outstd_logic);<br />ENDENTITY;<br />ARCHITECTURE rtl OFincomplete_assignmentIS<br />BEGIN<br /> process(sel, A, B)begin<br /> case(sel)is<br /> when"00"=><br /> O1 <= A;<br /> O2 <= A and B;<br /> when"01"=><br /> O1 <= B;<br /> O2 <= A xor B;<br /> when"10"=><br /> O1 <= A xor B;<br /> when"11"=><br /> O2 <= A or B;<br /> whenothers=><br /> O1 <= '0';<br /> O2 <= '0';<br /> endcase;<br /> endprocess;<br />ENDARCHITECTURE;<br />19<br />VHDL 360 ©<br />Do you think a Latch would be inferred in the below example?<br /><ul><li>Latches are inferred for both signals "O1" & "O2"
22. 22. Though the case is complete & no "null" statement is there, we find that "O1" & "O2" are not assigned in all case's branches  This is called “Incomplete signal assignment”</li></li></ul><li>Latch Inference<br />Most of the time latches are not desired in the design because they affect timing badly<br />To remove unintended latches: <br />Cover all branches of if-else and case statements<br />Avoid incomplete signal assignment by assigning a value to each signal in each branch<br />if you don’t care about other conditional values then assign the output to '0' or '1'<br />20<br />VHDL 360 ©<br />
23. 23. Enough CombinationalLet's Go Sequential<br />21<br />
24. 24. Sequential Logic<br />22<br />VHDL 360 ©<br /><ul><li>Let's model the well known D-FF with outputs Q & nQ and see the synthesis results</li></ul>Example 8:<br />Libraryieee;<br />useieee.std_logic_1164.all;<br />Entity d_ff is<br />Port(d, clk, rst :instd_logic;<br />Q, nQ :outstd_logic);<br />endentity;<br />Architecture behav of d_ff is<br />Begin<br />process(clk)<br />begin<br />If(rising_edge(clk))then<br />If(rst = '1')then<br /> Q <= '0';<br /> nQ <= '0';<br /> else<br /> Q <= d;<br /> nQ <=not (d);<br /> endif;<br /> endif;<br />endprocess;<br />end behav;<br />
25. 25. Sequential Logic<br />23<br />VHDL 360 ©<br /><ul><li>Let's model the well known D-FF with outputs Q & nQ and see the synthesis results</li></ul>Example 8:<br />Libraryieee;<br />useieee.std_logic_1164.all;<br />Entity d_ff is<br />Port(d, clk, rst :instd_logic;<br />Q, nQ :outstd_logic);<br />endentity;<br />Architecture behav of d_ff is<br />Begin<br />process(clk)<br />begin<br />If(rising_edge(clk))then<br />If(rst = '1')then<br /> Q <= '0';<br /> nQ <= '0';<br /> else<br /> Q <= d;<br /> nQ <=not (d);<br /> endif;<br /> endif;<br />endprocess;<br />end behav;<br />Two Flip-Flops ?!<br />Change the code to have only one Flip-Flop<br />
26. 26. Sequential Logic<br />24<br />VHDL 360 ©<br /><ul><li>Let's model the well known D-FF with outputs Q & nQ and see the synthesis results</li></ul>Example 9:<br />Libraryieee;<br />useieee.std_logic_1164.all;<br />Entity d_ff is<br />Port( d, clk, rst :instd_logic;<br /> Q, nQ :outstd_logic);<br />endentity;<br />Architecture behav of d_ff is<br />signal Q_int:std_logic;<br />Begin<br />process(clk)<br />begin<br />If(rising_edge(clk))then<br />If(rst = '1')then<br /> Q_int <= '0';<br /> else<br /> Q_int <= d;<br /> endif;<br /> endif;<br />endprocess;<br />Q <= Q_int;<br />nQ <=not (Q_int);<br />end behav;<br />Yep…That's what we want! <br />
27. 27. Sequential Logic<br />25<br />VHDL 360 ©<br /><ul><li>What about making an array of D-FFs?</li></ul>Example 10:<br />Libraryieee;<br />useieee.std_logic_1164.all;<br />Entity d_ffs is<br />Port(d: std_logic_vector(3downto0);<br />clk, rst :instd_logic;<br />Q, nQ :outstd_logic_vector(3downto0));<br />endentity;<br />Architecture behav of d_ffs is<br />signal Q_int:std_logic_vector(3downto0);<br />Begin<br />process(clk)<br />begin<br />If(rising_edge(clk))then<br />If(rst = '1')then<br /> Q_int <= (others => '0');<br /> else<br /> Q_int <= d;<br /> endif;<br /> endif;<br />endprocess;<br />Q <= Q_int;<br />nQ <=not (Q_int);<br />end behav;<br />
28. 28. Sequential Logic<br />Example 11: 8-bit Shift Register (Shift right)<br />Libraryieee;<br />useieee.std_logic_1164.all;<br />entity shift_register is<br /> Port( clk, D, enable :inSTD_LOGIC;<br /> Q :outSTD_LOGIC);<br />endentity;<br />architecture Behavioral of shift_register is<br />begin<br />process(clk)<br />variable reg:std_logic_vector(7downto0);<br />begin<br />ifrising_edge(clk)then<br />if enable = '1' then<br />for i in1to7loop<br /> reg(i-1):= reg(i);<br />endloop;<br /> reg(7):= d;<br />endif;<br />endif;<br /> Q <= reg(0);<br /> endprocess;<br />end Behavioral;<br />7 6 5 4 3 2 1 0<br />VHDL 360 ©<br />26<br />
29. 29. Flip-Flop Inference<br />Assignments under clock edge where the object value needs to be remembered across multiple process invocations  Flip-Flop<br />Signal assignment under clock edge will always infer a Flip-Flop<br />Variable assignment under clock edge will infer Flip-Flop only when its value ought to be remembered across process invocations<br />27<br />VHDL 360 ©<br />
30. 30. Exercise 1<br />LIBRARYieee;<br />USEieee.std_logic_1164.all;<br />Entity unknown is<br />port(x:outstd_logic;<br /> y:instd_logic_vector(3downto0);<br /> c:ininteger);<br />Endentity;<br />Architecture behave of unknown is<br />Begin<br /> x <= y(c);<br />End behave;<br />VHDL 360 ©<br />28<br />Deduce what the below code models<br />Use synthesis tool to validate your answer <br />