1st Semester M Tech CMOS VLSI Design (Dec-2013) Question Papers


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  • I am Studying Mtech 1st Semester can any one please send last three years Question papers for the below subjects in Embeded & VLSI design branch VLSI &Embedded System Design: 1) Microcontrollers for Embedded System design 2)Digital System Design 3) VLSI Technology and Design 4) CMOS Analog IC Design 5)CPLD and FPGA Architectures and Applications 6) CMOS Digital IC Design
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1st Semester M Tech CMOS VLSI Design (Dec-2013) Question Papers

  1. 1. f/ * USN /s f* tzBC021 I ( M.Tech. Degree Examination, Dec.2013 I Jan.20l4 GMOS VLSI Design Time: 3 Max. Marks:100 hrs. Note: Answer any FIVE o E E 0) () a. b. (Jx c. 69 .o' Derive the expression for the threshold voltage significaace of different parameters present in the Briefly .*p,F*- the fo llowing terms : i) il) Punch the (10 Marks) ,ii (06 Marks) , _ir . ^ Suppose Voo: l'.2Y andvt: 0.4V. Determine Vo,1in Fig.Q,'l(c) for i) V;, : 0V ; ii) Vi,= 0.6V ; iii) Vi" : 0.9V ; iv) V;n : 1.2Y. Neglect the bodyeffect. !'-J Vt', f I (04 Marks) 0.^t Frg Q 1(c) U() 6O o.o a. -d 2a 'ia o; tro. b. c. o.w oi 6.9 ! equation. , ,. ] -O E! d= of a MOS transistor and explain tlirough ionization. eoo .= c! (B$ ?a questions. Impact oo o full oil o.< (r >' bot tr5Q 3 a. b. c. qo tr> O. U< Consider the nMOS transistor in a 0.6pm process::with gate oxide thickness of 100A'. The doping level is Nn:2, I0'' cm-3 and the nominal threshold voltage is 0.7V. The body is tied to ground with a substrate contact. How much does the threshold change at room (07 Marks) temperature if the source is at 4V instead of OV? its significance in the design of an inverter base circuit. (07 Marks) Define noise margin and With relevant""response curves explain the transmission gate:: Oqlput characteristics for (06 Marks) change in control input and for change in switched input. Eesciibe in detail twin tub CMOS process of fabrication. Derive the expressions for rise time and fall time of a CMOS Obtain the scaling factors for the following: D Gate capacitance (C*) ii) Maximum operating frequency (fo). iii) Power dissipation per unit area (Pu). iv) Gate delay (T6). (08 Marks) (08 Marks) (04 Marks), o z L o. 4 a. b. Explain the phenomenon of charge storage and charge leakage and obtain the expression for (10 Marks) the holding time tmra. How do clocked SR and JK latch operate? Draw relevant waveforms. Draw NAND (10 Marks) implementation cut for both. I of2
  2. 2. r- tzBC02t 5 a. Calculate the Cin and Cout values of capacitance for the structure represented in Fig.Q.5(a). (08 Marks) <-----5oL x:- 1 l(#5o *-1.!3. -i Fie.Q.s(a) b. c. :' Derive the threshold voltage Vl for 2 input NOR gate. :'. (08 Marks) Draw nMOS and CMGS version of the circuit to realize the following Boolean expression. Z=A(D+E)+BC. 6a. b. c. Analyze a nMOS current mirror cirouit. (05 Marks) Explain the general principle of band gap reference and hence obtain the expression for Vss. (10 Marks) List out advantages of CMOS over nMOS. (05 Marks) 7a. b. 8a. b. c. (04 Marks) Mention the causes of latch up and guidelines for avoiding latch up. (10 Marks) (10 Marks) Describe charge sharing and its solution in brief. (05 Marks) Show how domino CMOS logic gate can be cascaded with static CMOS logic gates and also mention the limitation of the same. (05 Marks) , .t Describe different clock distribution schemes. (10 Marks)
  3. 3. tzECl29 USN M.Tech. Degree Examination, Dec.2013 I Jan-2O14 SOG Design Max. Marks:100 Time: 3 hrs. ,] Note: Answer uny FIYE d o o o. (.) ! (.) ! 8e bo-oo I a. full questions. What is Moore's law? What are the limitations impose by small device geometrics. Compare system-on-based, system-on-chip and system-on-package. (15 Marks) (05 Marks) 2 a. b. What is short channel effect? Explain. What is scaling? What are its types? Explain constant voltage scaling. (10 Marks) (10 Marks) 3 a. Consider an n-channel MOS process with the following parameters : substrate doping =2x1020cm-3, gate ilicon sate doping de,1sit1 density No =10'ucm'3, polysilicon gate doping b. )r!*-".) and oxide-interface fixed gl-rarge^density N6y : 4 x 1010 oxide thickness tox : 50 "m' is source and drain difhrsion doping density Np =,'f'6lz c*'. In addition, the channel region implanted with p-type impurities (impurity concentration N1 : 2x10"cm-2) to adjust the I Ec€ r;r .= oi Ho OE: -o threshold voltage. The junction depth of the source and drain diffusion regions is x.i : 1.0 pm.Plot the variation of the zero-bias threshold voltage Vro es a function of the channel length (assume that Vps = Vss : 0 and the threshold voltage without the channel a= design (ii) Soft IP versus Hard IP. oO 6O b. o0c 4 a. b. Explain waterfall versus spiial system design flow. Explain system design process. 5 a. What is flash memory? Explain NOR flash memory cell and pompare with NAND flash !6= LO o€ d.e o= 4tE L() v, ^;o EO0 o= *o tr> ^-o o- e< Z ]i (10 Marks) (10 Marks) b. o'v o o 'i '','. (10 Marks) memory cell. What is DRAM? Explain with the a. b. What is network topology? Explain. WMt are switching strategies? Explain packet switching and its types. (10 Marks) (10 Marks) a. b. What are the limitations of traditional ASIC design? Explain extensible processors as an alternative to RTL. (10 Marks) (10 lllarks) a. b. Explain design of timing closure: logic design issues. What is routing? Explain NOC routing and its schemes. (10 Marks) JO + Explain : (i) Canonical SOC a.l (10 Marks) design. (10 Marks) (10 Marks)
  4. 4. 12EC118 USN M.Tech. Degree Examination, Dec.2013 I Jan.2ol4 Advanced Embedded System Max. Marks:100 Time: 3 hrs. Note: Answer any FIVEfull questions. o o ! a I a. b. c. Distinguish between Big-Endian and Little-Endian processors, with an example. Explain the different types of RAM used for embedded system design. Describe the role of Brown-Out protection circuit. 2 a. () Explain,the operation of the 12C on-board communication interface; with a discussion on (08 Marks) the sequenee of operations required. (06 Marks) Discuss ZigBee network model. Explain the important operational quality attributes to be ,considered in any embedded (.) () ! oX b. L. ': " system design. , (06 Marks) (08 Marks) (06 Marks) (06 Marks) 6v coo .= c.l a. b. Compare dataflow graph"(DFG) and control data flowgraph (CDFG) model. (06 Marks) Design an embedded system for driver/passenger 'seat belt warning' in an automotive using (08 Marks) FSM model implement wait state using timer, What is UML? What are the fundamental building blocks of UML? Explain sequence (06 Marks) diagram, with an example. ,, Ho oE eO c. o> (,) = 6: 4a. oO b. o0c c. (06 Marks) Discuss "super-loop" based embedded firm ware design. With a neat diagram, explain the conversion process of a high level language to machine language. Also explain the advantages of high level language based development. (10 Marks) (04 Marks) What is "inline assemblv"? .:..::. Ed io oj= 5a. b. :q o! oio= AE C.E G; !o )E >,q oo' -bo o= *o :o o J< o o a.l c. (06 Marks) What is dead lock? Explain Coffman conditions favoring dead locks. b, ,, What is semaphore? Compare 'binary semaphore' and 'counting semaphore'. (06 Marks) (08 Marks) i, Describe the role of device driver in the OS context. 6 a. 1 a. i b. c. z o (06 Marks) Explain the round ,obin pro..ss scheduling. Three processes P1,'Pi, P3 with estimated completion time 10;, J, 7 ms respectively enters the ready queue togbtlier. Calculate Waiting Time (WT) and Turn Around Time (TAT) for each process. Also calculate average WT and average TAT in SJF (Shortest Job First) algorithm. (08 Marks) (06 Marks) Differentiate between threads and processes. a. b. c. d. and also discuss the advantages of (06 Marks) simulator firmware debugging. (08 Marks) Explain the 'Boundary Scan' based hardware debugging. (06 Marks) Describe the role of 'Monitor program' in frmware debugging. List down the features of simulator based debugging Write short notes on: RPC (Remote Procedure call). PLD (Programmable Logic Devices). Java for embedded development. Object-OrientedModel. (20 Marks)
  5. 5. 12E,C130 USN M.Tech. Degree Examination, Dec.2013 /Jan.20l4 VLSI Design Verification ::: Time: 3 hrs. Max. Marks:100 Note: Answer any o o o (! c! (J = () I a. b. c. 2a.Describe1ittinqproceSS,withhelpoffollowingcode: module abc (a, b, input a. b: output c: reg c: ! !,2 G,U -.o if ool trca .=N 6$ ":';""tt:'t":t (a::2'b01) c (: T'blj c -O oc) 60 c); . ' if 16: T'b0) ts() (.)tr a= questions. Discuss the importance of verification in VLSI design. Why formal methods are a preferred (10 Marks) way of verification? (05 Marks) How verification time may be reduced? (05 Marks) What is reconvergent model of verification? Give some examples. oX ou: FIVEfull b. c. 3 a. botr : T',b0: end module Compare testing and verification. Briefly explain the model checking (10 Marks) pto'Cess. (05 Marks) (05 Marks) Explain the terms: i) FSM coverage" ii) Statement coverage and iii) Transition coverage. ,6 E6 -?o 'Ca Write a test for the following FSM. State any assumptions made. a-=l OE 4=l ^X ().l 9E ao atE !o 5.v >' (F cov C OIJ o= o-B tr> o (10 Marks) b. o. 4a. J< - Crl o o Z o a b. c. What are code metrics? Give some examples. Discuss how ASIC verification is performed. For the following code, write verification code. Highlight its statement coverage. module HA (a, b, c, s) input a, b; output c, s; reg c, s; xor (s, a, b); and (c, a, b); end module Give schematic of a typical RC timing model of a CMOS gate. What is unateness of a signal? Explain with suitable waveforms. (05 Marks) (05 Marks) Marks) (05 Marks) (05 Marks)
  6. 6. 12EC130 5a. Justify the need for a verification specification document. Describe its functionality and (10 Marks) usage. (05 Marks) Give an example of timing description of an output pin inNDLM format. What is the need for parasitic extraction and how it is used in back annotation? (05 Marks) b. c. ,:::::' '";;' 6 ."1d1" (05 Mnrks) (0b Mnrtg Discuss the effect of IR drop in signal integrity. b. Give an overview of design sign off process. $n Discuss various timing parameters used in a static timing analysis. .,rtg: ::Describe setup and hold times. d. a. , 7a. Whflengging of variables is critical for drawing a ROBDD? Draw R@Op for the function f = abc + a'bc'+ ab'c + ab'c' What are Slffi;polvers? ;' b. c. . .d' ,ir! l .tf j r,,"q5t Write short notes"@lury FOUR: 8 Equivalence a. b. c. d. "' ' 'i''Jrl' ':': ,(05'Marks) (05 Marks) ':" (05 Marks) (10 Marks) (05 Marks) 11,,,,,,.'',, checkilig_. :.ti Event based simulators ", i, Design rules for digital VLSI.,:'', Waveform skew measurements .'-'..., Antenna effects during plasma etch. ,,,,,4:'1 ", . e. f. (20 Marks) ' **rr*{< i- ' ,a , r'll'!'l1 '=t"''' - tt''t_ ::. "..;.""" ,"'= :.: ::. ' ' 'ltttt' 't ,' ) of) ..';.:,:,.,!!'
  7. 7. I tzF,.C12t USN M.Tech. Degree Examination, Dec.2013 I Jan.20l4 Digital System Design Using Verilog Time: 3 hrs. , d o o Max. Marks:100 anJ) FIVEfull questions. 2. Assume suitable data wherever required. -^' '_-:*-'-'.'- *-"-*:-- -'-:--- ' --'-' :'--'. - -'r-"' 3. Mention top level blocks with input-output,poris. Note: 1. Answer L E 1 a. o OJ Bq bo* Design the logic circuit shown in Fig.Q.1(a) for a night light that is lit only when the switch is ON and the light sensor shows that it is dark. The logic is to be realized using 2:1 MUX only. If there are three lamps in the room controlled using the same logic, how do you modify the circnit shown in Fig.Q.1(a). (10 Marks) 6v tl oo tr€ .= c noo Y() o= -o Fig.Q.1(a) b. With the help of a detailed flow chart, discuss VLSI design flow. Mention the importance of each step in design flow. (t0 Marks) 2a. Ink jet printer have six catridge's for different colored ink: Black, Cyan, Magenta, Yellow, Light Cyan and Light Magenta. A multibit signal in such a printer indicates selection of one of the colors. To print tlre colors stored in different drums drivers need to be enabled for each of the colors. i) Devise a minimal length code for the signal selection repre.senting each color. ii) Design the logic shown in Fig.Q.2(a) that can enable the'corresponding driver based on the multibit signal. ii| If the number of colors are increased from 6 to 8, discuss the necessary changes to be ,,m6de to the multibit signal and the logic. (10 Marks) a: oO do cat a6 'Ea Os sa oj o= AE !o x .!i >,t: oocoO .r.s* ,'^' t{l aJ= *o GEN1RAL LTBfiARY tr> VL o !.) < t'uiv Jc'i a crr an;51 . Fig.Q.21a) o o z j b. 3 a. b. Write a verilog code for l0:1 multiplexer using case statement. (10 Marks) Design a 4-brt unsigned combinational multiplier using 4-bit adder. Discuss fixed point and floating point number format with example. (10 Marks) I of2 (10 Marks)
  8. 8. rzECl2t flip-flop with clock enable, positive logic low outputs' It is illegal for asynchronous preset and clear and both u.tiu. high and active 4a. write verilog code for a positive b. edge triggered (10 Marks) boih preset and clear to be active together' r numbers a and. , Oerelop a datapath to perform coLplex multiplication of two complex ! : br + jbi. The data path need to perform sequential represented u, u : u, i lal ana b .o-pt.* multiplication, *ith shared ,.roui.., and register to store intermediate. results' its working p'i":.lPlt-' Mention the control signals for the sequential datapath and discuss {10 Marks) 54. rDesign a 64Kx 16bit composite -:::? using 16K x bit.memory component' (10 Marks) .8 in Table Q.5(b). b. Dev, a verilog code foi a32 x 7 bit Rom, that can store the data shown able Q.5(b Address Content Address Content 1111111 0000001 1.111 1 10 0000011 1111100 00001 1 1 1111000 0001111 0 1 2 3 "., 4 ;5 6 7 8 9 0011111 0111111 l.r 10-f5 '"1,6,31 0000000 1010101 (10 Marks) '. of each modules'. 6 a. Discuss the internal architecture of'FP'GA'highlighting the functionality . b. 7 a. b. (10 Marks) technique adopted to reduce ground bounce effect, diagr discuss the organization '' of a high performance computer with multipleltuses. ' embedded (08 Marks) of Write instructions tlrat increment a 16-bit unsigned inte$er stored in memory. The address the least signifieanr'bye is in 12. The most significant byt€ is.il the next memoti#iijl?} With a neat block ,:.. c. g a. b. , o,' (10 Marks) mention the Define signal integrity, discuss giound bounce issue in signal integrity and Discuss ttrO. l ortance of i cache memory, how is cache memo,rX,used i processof.".'' in a embedded (06Marks) Discuis physical design flow and mention the importance of floor planning in PhYsical ceslgn. ,Briehy discuss serial interface standards for I/O devices. Develop verilog code for 4-bit counter' ''........ i<*{<16* 1 (06 Marks) (06 Marks) (08 Marks)