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# 3Sem-Logic Design Notes-Unit4-Design and Analysis of Combinational Logic

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3Sem-Logic Design Notes-Unit4-Design and Analysis of Combinational Logic

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### 3Sem-Logic Design Notes-Unit4-Design and Analysis of Combinational Logic

1. 1.                                                 P e o p l e s   E d u c a t i o n   S o c i e t y   S o u t h   C a m p u s   ( w w w . p e s . e d u )   Prof  Shivananda  Koteshwar   E&C  Department,  PESIT  SC       Analysis  and  Design  of  Combinational  Logic  II   • Digital  multiplexers   • Using  multiplexers  as  Boolean  function  generators   • Adders  and  subtractors   • Cascading  full  adders                     • Look  ahead  carry       • Binary  comparators  Design     Reference  Books:   • “Digital  Logic  Applications  and  Design”,  John  M  Yarbrough,  Thomson  Learning,  2001   • “Digital  Principles  and  Design  “,  Donald  D  Givone,  Tata  McGraw  Hill  Edition,  2002     UNIT  4:     Analysis  and  design  of  combinational  logic  -­‐  II:  Digital  multiplexers-­‐  Using  multiplexers  as  Boolean   function  generators.  Adders  and  subtractors-­‐Cascading  full  adders,  Look  ahead  carry,  Binary   comparators.  [(Text  book  1)  4.5,  4.6  -­‐  4.6.1,  4.6.2,  4.7]             ODD   SEMESTER   13   LOGIC  DESIGN-­‐3-­‐CLASS  NOTES  –  UNIT4
2. 2. Logic  Design  (3rd  Semester)                                                                                                                            UNIT  4  Notes  v1.1       Prof  Shivananda  Koteshwar  ©                                                                                                                    shivoo@pes.edu  2   Multiplexer It is a combinational circuit that selects binary information from one of the input lines and directs it to a single output line Usually there are 2n input lines and n selection lines whose bit combinations determine which input line is selected For example for 2-to-1 multiplexer if selection S is zero then I0 has the path to output and if S is one I1 has the path to output
3. 3. Logic  Design  (3rd  Semester)                                                                                                                            UNIT  4  Notes  v1.1       Prof  Shivananda  Koteshwar  ©                                                                                                                    shivoo@pes.edu  3   Digital multiplexer provide the digital equivalent of an analog selector switch. A digital multiplexer connects one of n inputs to a single output line so that the logical value of the input is transferred to the output. The one of n input selection is determined by m select inputs where n=2m Several digital multiplexer are available – 74xx153 is a dual 4 to 1 mux, 74xx151 is a single 8 to 1 mux and 74xx150 is a single 16 to mux
4. 4. Logic  Design  (3rd  Semester)                                                                                                                            UNIT  4  Notes  v1.1       Prof  Shivananda  Koteshwar  ©                                                                                                                    shivoo@pes.edu  4   74xx151: Single 8:1 Notice that 1s and 0s are not present in the truth table output columns because MUX acts as a data switch and it does not generate any data of its own but passes external input data from the selected input to the output. When multiple digital signs need to be multiplexed at the same time, we use several multiplexers in parallel
5. 5. Logic  Design  (3rd  Semester)                                                                                                                            UNIT  4  Notes  v1.1       Prof  Shivananda  Koteshwar  ©                                                                                                                    shivoo@pes.edu  5   4 four-bit data sources multiplexed to a single four-bit destination
6. 6. Logic  Design  (3rd  Semester)                                                                                                                            UNIT  4  Notes  v1.1       Prof  Shivananda  Koteshwar  ©                                                                                                                    shivoo@pes.edu  6   4bit 4:1 Mux • To design a 4 bit 4:1 mux, we use four 4:1 mux or two dual 4:1 mux. Two 74S153 ICs (dual 4:1 mux) each containing a dual 4:1 mux is used to form the system • Enable and select are connected in parallel which means chips will be enabled and inputs selected together • All position 3 bits from each data source provide inputs to the top mux, all position 2 bits provide inputs to next mux and so on • Data source A is selected when select inputs BA=11, then all four individual mux switch the appropriate input bit to its output, creating a 4 bit destination
7. 7. Logic  Design  (3rd  Semester)                                                                                                                            UNIT  4  Notes  v1.1       Prof  Shivananda  Koteshwar  ©                                                                                                                    shivoo@pes.edu  7   32:1 Mux • Two 74xx150 16:1 mux can be used to form a 32:1 mux
8. 8. Logic  Design  (3rd  Semester)                                                                                                                            UNIT  4  Notes  v1.1       Prof  Shivananda  Koteshwar  ©                                                                                                                    shivoo@pes.edu  8   64:1 Mux • Four 74xx150 and a single 4:1 (1/2 of 74xx153 4:1) mux can combine to create a 64:1 mux • V and X are the select inputs to the mux system. They are decoded by 74xx139 to determine which of the four 8:1 mux will be enabled • Because only one of the four inputs from the decoder can be active (low), only one of the 8:1 mux can be enabled at a time • Select inputs X through Z are connected in parallel to the four mux ICs. The decoded select input switches the data input to the output of the enabled 8:1 mux • The top mux switches inputs D0 to D7 to the output. The next mux switches outputs D8 to D15 and son on • The four mux active low outputs are ORed together to provide a system of 1 of 32 output
9. 9. Logic  Design  (3rd  Semester)                                                                                                                            UNIT  4  Notes  v1.1       Prof  Shivananda  Koteshwar  ©                                                                                                                    shivoo@pes.edu  9   Using MUX as Boolean Function Generators A mux consists of a set of AND gates feeing a single output (N)OR gate. Because any Boolean function can be realized using AND-OR and NOT primitives, everything that is needed to realize a logic equation is found in a mux. Each AND gate in a mux can be used to generate a minterm when the number of variables in the minterm is equal to the number of select lines of the mux 8:1 mux has 3 select lines, so it can be used to generate up to 23 minterms. NOTE: • 3 variable Boolean equation requires 8:1 mux (74xx151) • 4 variable Boolean equation requires 16:1 mux (74xx150) • 5 variable Boolean equation requires 1:32 mux
10. 10. Logic  Design  (3rd  Semester)                                                                                                                            UNIT  4  Notes  v1.1       Prof  Shivananda  Koteshwar  ©                                                                                                                    shivoo@pes.edu  10   How to implement 4 variable Boolean question with 8:1 mux? 4 variable Boolean equation requires 16:1 mux (74xx150). But if we want to use 8:1 mux (74xx151), we have to connected the mux data inputs to 0,1,variable or complemented variable 3 variables are used as select inputs and the fourth variable is connected as needed to the mux data inputs Example1: T = f(w,x,y,z) = min (0,1,2,4,5,7,8,9,12,13), A 4 variable equation using 8:1 mux? • Look at the column z (input) and T (output) • First 2 rows, irrespective of z, T is 1 so MEV=1 • 3rd and 4th row, T is complement of z so MEV=z’ • 5th and 6th row, T is 1 irrespective of z, so MEV=1 • 7th and 8th row, T is z so MEV = z and so on
11. 11. Logic  Design  (3rd  Semester)                                                                                                                            UNIT  4  Notes  v1.1       Prof  Shivananda  Koteshwar  ©                                                                                                                    shivoo@pes.edu  11   Example2: Realize S=f(a,b,c,d,e) = min(8,9,10,11,13,15,17,19,21,23,24,25,26,27,29,31) using least number of ICs S= ae + bc’ + be • 4 variable remain after simplification (it was 5 initially) • Easy way is to implement it using 16:1 mux but lets use 8:1 mux • This is achieved by using select inputs for 3 variables and fourth variable is connected as needed to the mux data inputs
12. 12. Logic  Design  (3rd  Semester)                                                                                                                            UNIT  4  Notes  v1.1       Prof  Shivananda  Koteshwar  ©                                                                                                                    shivoo@pes.edu  12   b c e a T MEV 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 1 1 a 0 1 0 0 0 0 1 0 1 0 0 0 1 1 0 0 0 1 1 1 1 a 1 0 0 0 1 1 0 0 1 1 1 1 0 1 0 1 1 0 1 1 1 1 1 1 0 0 0 1 1 0 1 0 0 1 1 1 0 1 1 1 1 1 1 1
13. 13. Logic  Design  (3rd  Semester)                                                                                                                            UNIT  4  Notes  v1.1       Prof  Shivananda  Koteshwar  ©                                                                                                                    shivoo@pes.edu  13   NOTE: 1. One can always use any 3 variables for select inputs and fourth one for mux data input. 2. Make sure you remember the ordering (LSB-MSB) of select inputs 3. In the table, we have used alternately a, b, c for select inputs and e for mux data input a b c e T MEV 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 0 1 0 1 0 1 1 1 0 1 1 0 1 0 1 1 1 1 1 1 0 0 0 0 1 0 0 1 1 e 1 0 1 0 0 1 0 1 1 1 e 1 1 0 0 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1
14. 14. Logic  Design  (3rd  Semester)                                                                                                                            UNIT  4  Notes  v1.1       Prof  Shivananda  Koteshwar  ©                                                                                                                    shivoo@pes.edu  14   Lets try to expand this method and see if we can use a 4:1 mux instead of a 8:1 mux! Closer look at the k-maps for S we can deduce that, • When be=00, S=0 • When be=01, S=a • When be=10, S=c’ • When be=00, S=1
15. 15. Logic  Design  (3rd  Semester)                                                                                                                            UNIT  4  Notes  v1.1       Prof  Shivananda  Koteshwar  ©                                                                                                                    shivoo@pes.edu  15   NOTE • In this example, why did we choose b & e as the select signals and a & c as the data inputs? • The table show all combination of possible select inputs and resulting inputs to the 4:1 mux • We will select the best one which uses simple variables and not any additional combinational logic. Looking at the table, we can see that E is the best (b and e as select signal)
16. 16. Logic  Design  (3rd  Semester)                                                                                                                            UNIT  4  Notes  v1.1       Prof  Shivananda  Koteshwar  ©                                                                                                                    shivoo@pes.edu  16   Half Adder A half adder adds two one-bit binary numbers A and B. It has two outputs, S and C. Half adders cannot be used compositely, given their incapacity for a carry-in bit.
17. 17. Logic  Design  (3rd  Semester)                                                                                                                            UNIT  4  Notes  v1.1       Prof  Shivananda  Koteshwar  ©                                                                                                                    shivoo@pes.edu  17   Full Adder A full adder adds binary numbers and accounts for values carried in as well as out. A one-bit full adder adds three one-bit numbers, often written as A, B, and Cin; A and B are the operands, and Cin is a bit carried in.
18. 18. Logic  Design  (3rd  Semester)                                                                                                                            UNIT  4  Notes  v1.1       Prof  Shivananda  Koteshwar  ©                                                                                                                    shivoo@pes.edu  18
19. 19. Logic  Design  (3rd  Semester)                                                                                                                            UNIT  4  Notes  v1.1       Prof  Shivananda  Koteshwar  ©                                                                                                                    shivoo@pes.edu  19   Full Adder with 2 Half Adders
21. 21. Logic  Design  (3rd  Semester)                                                                                                                            UNIT  4  Notes  v1.1       Prof  Shivananda  Koteshwar  ©                                                                                                                    shivoo@pes.edu  21   Propagation Delay: Total adder delay is the product of the sum of the number of stages in the adder and the carry-in to carry-out propagation delay time. The carry-in to carry-out propagation delay is used instead of the input-to-sum output delay because it is the signal that ripples from one full adder to another.
23. 23. Logic  Design  (3rd  Semester)                                                                                                                            UNIT  4  Notes  v1.1       Prof  Shivananda  Koteshwar  ©                                                                                                                    shivoo@pes.edu  23   • pi = xi XOR yi : pi is called the propagate term ci+1 = gi + pici Generate Term: gi = xiyi • gi is known as the carry generate signal since a carry (ci+1) is generated whenever gi =1, regardless of the input carry (ci). Propagate Term: pi = xi XOR yi • Mostly, we only care about propagating a 1. We're not that concerned about propagating 0's. That's why we AND pi to ci. • By itself, pi may not cause a carry (pi is 1 only if either xi or yi is 1) . However, it can propagate a carry-in of 1, by causing a carry-out of 1, if pi is 1. Propagating a carry means to move the carry from the previous adder to the next adder Why generate and carry? If you look at the Boolean expressions for pi and gi, you will see that they both use only xi and yi. Neither depends on the carry. Since xi and yi are available immediately, this gives us hope that we can avoid waiting for carries This is how we do it. First, let's write the c1 which is the carry out for the adding bit 0 of x and y c1 = g0 + p0c0 c2 = g1 + p1c1= g1 + p1(g0 + p0c0) = g1 + p1g0 + p1p0c0 Notice that we no longer have c1. That means we no longer have to wait for the carry! Again, we would prefer to avoid using c2 since this requires us to wait for the result to propagate across two adders. However, we already have a Boolean expression for c2 that doesn't use any carries except c0 , which we have right away c3 = g2 + p2c2 = g2 + p2(g1 + p1g0 + p1p0c0) = g2 + p2g1 + p2p1g0 + p2p1p0c0
24. 24. Logic  Design  (3rd  Semester)                                                                                                                            UNIT  4  Notes  v1.1       Prof  Shivananda  Koteshwar  ©                                                                                                                    shivoo@pes.edu  24   Already, you should be able to detect a pattern. By following the same pattern, you'd expect: c4 = g3 + p3g2 + p3p2g1 + p3p2p1g0 + p3p2p1p0c0 Quick relook at the equations: Ci+1 = AiBi + BiCi + Ci Ai Ci+1 = AiBi + Ci (Ai XOR Bi) Gi = Ai.Bi Pi = (Ai XOR Bi) C1 = G0 + P0.C0 C2 = G1 + P1.C1 = G1 + P1.G0 + P1.P0.C0 C3 = G2 + P2.G1 + P2.P1.G0 + P2.P1.P0.C0 C4 = G3 + P3.G2 + P3.P2.G1 + P3P2.P1.G0 + P3P2.P1.P0.C0 Si = Ai XOR Bi XOR Ci Si = Pi XOR Ci Boolean expressions are expressed as SOP function of C0 rather than its preceding carry signal. Since its in SOP form, we can represent the Carry Lookahead block in 2 level logic circuits. So the entire 4 bit CLA can be represented in 3 levels of logic. Propagation Delay in CLA First level: Generates all the P & G signals. Four sets of P & G logic (each consists of an XOR gate and an AND gate). Output signals of this level (P’s & G’s) will be valid after 1τ Second level: The Carry Look-Ahead (CLA) logic block which consists of four 2-level implementation logic circuits. It generates the carry signals (C1, C2, C3, and C4) as defined by the above expressions. Output signals of this level (C1, C2, C3, and C4) will be valid after 3τ Third level: Four XOR gates which generate the sum signals (Si) (Si = Pi XOR Ci). Output signals of this level (S0, S1, S2, and S3) will be valid after 4τ
25. 25. Logic  Design  (3rd  Semester)                                                                                                                            UNIT  4  Notes  v1.1       Prof  Shivananda  Koteshwar  ©                                                                                                                    shivoo@pes.edu  25   Comparing CLA and Ripple Carry Adder: Delay • For a 4 bit adder, 4 Sum signals (S0, S1, S2 & S3) will all be valid after a total delay of 4τ in CLA • For a 4-bit adder (n = 4), the Ripple Carry adder delay is 9τ as its (2n+1) τ Area • The disadvantage of the CLA adders is that the carry expressions (and hence logic) become quite complex for more than 4 bits.
26. 26. Logic  Design  (3rd  Semester)                                                                                                                            UNIT  4  Notes  v1.1       Prof  Shivananda  Koteshwar  ©                                                                                                                    shivoo@pes.edu  26   HALF SUBTRACTOR
27. 27. Logic  Design  (3rd  Semester)                                                                                                                            UNIT  4  Notes  v1.1       Prof  Shivananda  Koteshwar  ©                                                                                                                    shivoo@pes.edu  27
28. 28. Logic  Design  (3rd  Semester)                                                                                                                            UNIT  4  Notes  v1.1       Prof  Shivananda  Koteshwar  ©                                                                                                                    shivoo@pes.edu  28   COMPARATOR A binary magnitude comparator is a logic circuit that provides output information indicating the relative magnitude of two input operandi. Three output conditions exist as a result of comparison of two operands: A=B, A>B and A<B 1 bit Comparator
29. 29. Logic  Design  (3rd  Semester)                                                                                                                            UNIT  4  Notes  v1.1       Prof  Shivananda  Koteshwar  ©                                                                                                                    shivoo@pes.edu  29   2-bit Comparator A=B, f(a1,a0,b1,b0) = min(0,5,10,15) =a1’a0’b1’bo’ + a1’a0b1’b0 + a1a0b1b0 + a1a0’b1b0’ A>B, f(a1,a0,b1,b0) = min(4,8,9,12,13,14) = a1b1’ + a0b1’b0’ + a1a0b0’ A<B, f(a1,a0,b1,b0) = min(1,2,3,6,7,11) = a1’b1 +a1’a0’bo + a0’b1b0 (Write the Logic Circuit Diagram)
30. 30. Logic  Design  (3rd  Semester)                                                                                                                            UNIT  4  Notes  v1.1       Prof  Shivananda  Koteshwar  ©                                                                                                                    shivoo@pes.edu  30   4-bit Comparator Increasing the size of the comparator beyond two bits would produce a bulky truth table. Similar to design of a multi-bit full- adder, we can cascade single cell/stage comparators to get a multi size comparator. The technique of designing a single cell, each with a set of inputs and outputs, and then cascading the cells to form larger circuits is called iterative design Two classes of inputs and outputs exist: • primary inputs/outputs enter/exit the cell from/to external data sources/destinations • secondary inputs/outputs enter/exit the cell from/to neighboring cells which communicate information between cells Primary input to a comparator cell Cj are provided from external data sources (Aj and Bj). Comparator secondary output, Soj conveys to cell; Cj+1 the results of the comparison up to that cell position. No primary outputs are necessary for individual comparator cells because all cells must respond before the final result can be known
31. 31. Logic  Design  (3rd  Semester)                                                                                                                            UNIT  4  Notes  v1.1       Prof  Shivananda  Koteshwar  ©                                                                                                                    shivoo@pes.edu  31   Designing a 4 bit comparator using iterative design methodology Lets design those individual blocks (Comparator Cell) used iteratively • The inter-cell secondary inputs and outputs are encoded. Using two bit so that three pieces of information (A=B, A<B, A>B) can be economically conveyed • All the comparator cells are identical. The least significant cell has its secondary inputs grounded. Here this indicates A=B. Each cell compares the external data it receives, checks the result from previous cells, and then transmits the result to the next cell • A code must be assigned to the two secondary input/output signals from each cell. Let SO2 be defined as secondary output 2. SI1 be defined as secondary input 1 and so on. The secondary inputs and outputs are connected between cells
32. 32. Logic  Design  (3rd  Semester)                                                                                                                            UNIT  4  Notes  v1.1       Prof  Shivananda  Koteshwar  ©                                                                                                                    shivoo@pes.edu  32
33. 33. Logic  Design  (3rd  Semester)                                                                                                                            UNIT  4  Notes  v1.1       Prof  Shivananda  Koteshwar  ©                                                                                                                    shivoo@pes.edu  33   Comparator Cell: The secondary outputs connecting are encoded. To determine the result of a N-bit comparison, the final secondary outputs must be decoded to produce A=B, A>B and A<B boundary outputs
34. 34. Logic  Design  (3rd  Semester)                                                                                                                            UNIT  4  Notes  v1.1       Prof  Shivananda  Koteshwar  ©                                                                                                                    shivoo@pes.edu  34
35. 35. Logic  Design  (3rd  Semester)                                                                                                                            UNIT  4  Notes  v1.1       Prof  Shivananda  Koteshwar  ©                                                                                                                    shivoo@pes.edu  35   N-Bit Comparator Design Using 4 bit comparators, we can expand to 8 bit comparator or more.
36. 36. Logic  Design  (3rd  Semester)                                                                                                                            UNIT  4  Notes  v1.1       Prof  Shivananda  Koteshwar  ©                                                                                                                    shivoo@pes.edu  36   1. Designing a comparator to check if n bit numbers are equal. Configure this using cascaded 1 bit equality comparator Comparing two n-bit numbers for their equality • A ----> An-1 An-2 …………A0 • B ----> Bn-1 Bn-2………….B0 Algorithm: 1. Start with MSB and compare one bit at a time 2. If the bit of one number is greater than the corresponding bit of the other number, then the number is greater. This becomes the solution 3. Else, i.e. if the two bits are equal, then compare the next bit. 4. Repeat till you cover all the bits Design 1-bit comparator forms the building block for comparing two n-bit numbers. • E is the cascading signal • Ei+1 is the Cascading input, Ei is the cascading output • Ei+1 = 1 implies that the two numbers are not equal so far • Ei+1 = 0 implies that the two numbers are equal so far • If Ei+1 = 1, then Ei = 1, Else, Ei = Ei+1 + (Ai XOR Bi ) • Using this building block, we can build an n-bit comparator circuit • En=0
37. 37. Logic  Design  (3rd  Semester)                                                                                                                            UNIT  4  Notes  v1.1       Prof  Shivananda  Koteshwar  ©                                                                                                                    shivoo@pes.edu  37   • The final result is, if E0 = 0, then A = B and if E0 = 1, then A != B