User Defined Rules( UDR’s) – Written for Lintra using Lira API’s to check on waiver/errors. Lira (System LINTRA – RTL Data Base UNIX Indicators Verilog linting tool. ( My SQL) Environ (DB Compiler) – (Check for ment Center) Has a set of violations.) defined API’s in Perl/C++.INTEL INTERNSHIP SUMMER 2011CURRENT INDICATOR SYSTEM IN INTELEVERY PROJECT HAS ITS OWN DATABASE.- NEED TO WRITE SCRIPTS AND INDICATORS.- CREATE DISC SPACE- MANAGE DATABASE- MORE TIME CONSUMING------Black Box--------- --- Back End--Front EndLearning - Perl Scripting , Tool Flows, Working of different timezones
User Defined Rules( UDR’s) – Written for Lintra using Lira APO’s to check on waiver/errors. Lira (System LINTRA – RTL iBI Data Power Indicators Verilog linting tool. Base ( Pivot PUMA Compiler) – (Check for MSSQL) (Excel (Performance Has a set of violations.) - One Plugin) Unified defined API’s centralized Measurement in Perl/C++. DB for all Application) projects data Gate Keeper( ibI Tool used to logg track Turnins er (Code change set)INTEL INTERNSHIP FEB –MAY 2012NEW INDICATOR SYSTEM IN INTEL- ONE DATABASE FOR ALL PROJECTS- ABILITY TO DRILL DOWN TO ROOT CAUSE- USES EXCEL PLUGINS TO CREATE DASHBOARDS- SUPPORTED BY IT------Black Box--------- --- Back End--Front EndLearning - MSSQL queries, Debugging scripts, Implementing new tool flow
INTEL INTERNSHIP MAY 2012 ONWARDS- Create a cloud based solution for current SMB’s using Nirvanix Api’s.- Virtualize servers for Windows machines.- Sync workstations/ Servers using Rsync.
RESEARCH ASSISTANT – SMART GRID CENTER, CSUS Smart Grid - A smart grid is a digitally enabled electrical grid that gathers, distributes, and acts on information about the behavior of all participants (suppliers and consumers) in order to improve the efficiency, importance, reliability, economics, and sustainability of electricity service that gathers, distributes, and acts on information about the behavior of all participants (suppliers and consumers) in order to improve the efficiency, importance, reliability, economics, and sustainability of electricity services. OSI Soft – SCADA data analysis software. FOA 152 – Employee Retraining in Power industry sector. IEEE Region 6 webmaster. CSUS – EEE/CPE webmaster.
FIFO – BASED ON SYSTEM VERILOG DESIGN / VERIFICATION 1-bit input flush: clears every location in the FIFO 1-bit input insert: When asserted, data on data_in is stored at the tail of FIFO on posedge of clock 1-bit input remove: When asserted, data at the head of the FIFO is removed from the FIFO and placed on the on data_out output port on positive edge of clock 32-bit input data_in: input data port 32-bit output data_out: output data port 1-bit output full: asserted on the positive edge of clock when the buffer is full and there is no more room for data 1-bit output empty: asserted on positive edge of clock when the buffer is empty (no data in the buffer) Full and empty flags are used by the external environment for proper use of the FIFO Develop a System Verilog interface that can be used in the FIFO (DUT) and the test bench environment. Utilize the class concept to fully test the functionality Develop a System Verilog program block for testing the FIFO.
PCI DESIGN Designing Master/Target handshake for a PCI device involving a memory write with three data phases for an optimized address at a PCI clock 33MHZ providing test bench and simulation results. Block diagram (high-level design), state machine, and program code In the verilog design we have made an initiator and target device to do 3 optimized write phases. The signal values are checked at the positive edge of clock and driven on the negative edge as required in PCI specs.
PARALLEL PIPELINED MATRIX MULTIPLIER A and B are pre-stored in memory. Elements of A, B, and P are 32-bit integers. P should be stored in memory. You can have up to four 32-bit wide memory banks. Address port for a memory bank is 32-bit.. Memory bank gets proper control and address signals, it needs 8 cycles to retrieve or write 32 bits. The address phase takes one cycle. Arithmetic unit can only operate on register-type data. The results of the ALU cannot directly be written into the memory block. The multiplication of two matrices A and B will begin when an input signal called START is asserted. PMM will assert and output signal called “DONE” when multiplication is done. Develop a test bench for validating the data path. Synthesize PMM and analyze the synthesized circuit using Synopsis Design Compiler tool. VCS - Verilog Simulator – simulate / Code Coverage. VCS – Design Complier – Synthesis Tool. VCS – Design vision – Interface to communicate with the DC. 1.ADDRESS_STORE_A 2. ADDRESS_STORE_B_EVEN ,ADDRESS_STORE_B_ODD 3. DATA_MATRIX_A - A[7:0],A[15:8],A[23:16],A[31:24] 4. DATA _MATRIX_B - B_EVEN,B_ODD 5. DATA_MUL_A 6. DATA_MUL_B 7. MUL_OUTPUT 8. ADD_OUTPUT 9. EXEC_MEM_P_EVEN 10. EXEC_MEM_P_ODD 11. EXEC_MEM_P_EVEN 12. EXEC_MEM_P_ODD 13.MEM_WB_P_EVEN 14. MEM_WB_P_ODD 15. REG_OUTPUT 16.TEMP_REGISTER_EVEN TEMP_REGISTER_ODD 17. TEMP_REGISTER_EVEN [31:0] TEMP_REGISTER_EVEN [63:32] TEMP_REGISTER_ODD[31:0] TEMP_REGISTER_ODD [63:32] 18. DATA_MATRIX_P
STANDARD CELL LIBRARY Design and layout digital standard cell library in 90nm CMOS using Microwind CAD tool involving basic and complex CMOS logic gates without DRC error. Technology file called “cmos90n.rul”. Minimize the area used. VDD bus on top and a GND bus on the bottom of the cell, with each bus made out of metal 6 which is 5µm wide. All cell inputs and outputs other than VDD and GND should come out to the bottom of the cell in metal 3. Route connections using metal such that even metals route horizontal and odd metals route vertical. Devices as small as possible. Metal routing as close.
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