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The increasing use of diverse architectures resulting in heterogeneous platforms for High-Performance Computing (HPC) presents a significant programming challenge. The resultant design productivity gap is a bottleneck to achieving the maximum possible performance. Our current work aims to address this design productivity gap specifically for FPGAs, where it is a major obstacle to their wider adoption in HPC.
We will present the TyTra design flow, which is being developed in the context of our larger project that aims to create a turn-key compiler for heterogeneous target platforms.
We will discuss an evolving custom high-level language, the TyTra language, that facilitates generation of different correct-by-construction program variants through type- transformations.
We will then talk about the custom target intermediate language for the high-level TyTra language, the Tytra-IR, which is similar to LLVM, but is extended to include explicit parallelization semantics that enable it to describe the different configurations associated with each program variant. It also allows direct association of each of them with an accurate estimate of cost and performance. We will briefly discuss this cost model and our on-going work with an estimator and code generator for FPGAs.