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- 1. Contemporary Logic Design Finite State Machine DesignChapter #8: Finite State Machine Design Contemporary Logic Design Randy H. Katz University of California, Berkeley June 1993 © R.H. Katz Transparency No. 8-1
- 2. Contemporary Logic DesignMotivatio Finite State Machine Designn • Counters: Sequential Circuits where State = Output • Generalizes to Finite State Machines: Outputs are Function of State (and Inputs) Next States are Functions of State and Inputs Used to implement circuits that control other circuits "Decision Making" logic • Application of Sequential Logic Design Techniques Word Problems Mapping into formal representations of FSM behavior Case Studies © R.H. Katz Transparency No. 8-2
- 3. Contemporary Logic DesignChapter Overview Finite State Machine DesignConcept of the State Machine • Partitioning into Datapath and Control • When Inputs are Sampled and Outputs AssertedBasic Design Approach • Six Step Design ProcessAlternative State Machine Representations • State Diagram, ASM Notation, VHDL, ABEL Description LanguageMoore and Mealy Machines • Definitions, Implementation ExamplesWord Problems • Case Studies © R.H. Katz Transparency No. 8-3
- 4. Contemporary Logic DesignConcept of the State Finite State Machine DesignMachineComputer Hardware = Datapath + Control QualifiersRegisters FSM generating sequencesCombinational Functional of control signals Units (e.g., ALU) Instructs datapath what toBusses do next Control Control "Puppeteer who pulls the strings" State Qualifiers Control and Signal Inputs Outputs "Puppet" Datapath © R.H. Katz Transparency No. 8-4
- 5. Contemporary Logic DesignConcept of the State Finite State Machine DesignMachine Example: Odd Parity Checker Assert output whenever input bit stream has odd # of 1s Reset Present State Input Next State Output Even 0 Even 0 0 Even 1 Odd 0 Even [0] Odd 0 Odd 1 Odd 1 Even 1 1 1 Symbolic State Transition Table Odd [1] Present State Input Next State Output0 0 0 0 0 0 1 1 0 1 0 1 1 State 1 1 0 1 Diagram Encoded State Transition Table © R.H. Katz Transparency No. 8-5
- 6. Contemporary Logic Design Concept of the State Finite State Machine Design Machine Example: Odd Parity Checker Next State/Output Functions NS = PS xor PI; OUT = PS Input Output NS T QInput CLK D Q PS/Output CLK Q Q R R Reset Reset D FF Implementation T FF Implementation Input 1 0 0 1 1 0 1 0 1 1 1 0 Clk Output 1 1 1 0 1 1 0 0 1 0 1 1 Timing Behavior: Input 1 0 0 1 1 0 1 0 1 1 1 0 © R.H. Katz Transparency No. 8-6
- 7. Contemporary Logic DesignConcept of State Finite State Machine DesignMachine Timing: When are inputs sampled, next state computed, outputs asserted? State Time: Time between clocking events • Clocking event causes state/outputs to transition, based on inputs • For set-up/hold time considerations: Inputs should be stable before clocking event • After propagation delay, Next State entered, Outputs are stable NOTE: Asynchronous signals take effect immediately Synchronous signals take effect at the next clocking event E.g., tri-state enable: effective immediately sync. counter clear: effective at next clock event © R.H. Katz Transparency No. 8-7
- 8. Contemporary Logic Design Concept of State Finite State Machine Design Machine Example: Positive Edge Triggered Synchronous System State Time On rising edge, inputs sampled outputs, next state computed After propagation delay, outputs and next state are stableClock Immediate Outputs: affect datapath immediatelyInputs could cause inputs from datapath to change Delayed Outputs: take effect on next clock edgeOutputs propagation delays must exceed hold times © R.H. Katz Transparency No. 8-8
- 9. Contemporary Logic DesignConcept of the State Finite State Machine DesignMachine Communicating State Machines One machines output is another machines input X CLK FSM 1 FSM 2 Y FSM1 A A B X Y=0 X=0 Y=0 X=0 A C FSM2 C D D [1] [0] X=1 Y Y=1 X=1 B D Y=0,1 [0] X=0 [1] Machines advance in lock step Initial inputs/outputs: X = 0, Y = 0 © R.H. Katz Transparency No. 8-9
- 10. Contemporary Logic DesignBasic Design Approach Finite State Machine Design Six Step Process 1. Understand the statement of the Specification 2. Obtain an abstract specification of the FSM 3. Perform a state mininimization 4. Perform state assignment 5. Choose FF types to implement FSM state register 6. Implement the FSM 1, 2 covered now; 3, 4, 5 covered later; 4, 5 generalized from the counter design procedure © R.H. Katz Transparency No. 8-10
- 11. Contemporary Logic DesignBasic Design Approach Finite State Machine Design Example: Vending Machine FSM General Machine Concept: deliver package of gum after 15 cents deposited single coin slot for dimes, nickels no change Step 1. Understand the problem: Draw a picture! Block Diagram N Coin Vending Open Gum Sensor D Machine Release Reset FSM Mechanism Clk © R.H. Katz Transparency No. 8-11
- 12. Contemporary Logic DesignVending Machine Finite State Machine DesignExample Step 2. Map into more suitable abstract representation Tabulate typical input sequences: three nickels nickel, dime dime, nickel Reset two dimes S0 two nickels, dime N D Draw state diagram: S1 S2 Inputs: N, D, reset Output: open N D D N S3 S4 S5 S6 [open] [open] [open] N D S7 S8 [open] [open] © R.H. Katz Transparency No. 8-12
- 13. Contemporary Logic DesignVending Machine Finite State Machine DesignExample Step 3: State Minimization Present Inputs Next Output Reset 0¢ State D N State Open 0¢ 0 0 0¢ 0 N 0 1 5¢ 0 5¢ 1 0 10¢ 0 D 1 1 X X 5¢ 0 0 5¢ 0 N 0 1 10¢ 0 10¢ 1 0 15¢ 0 D 1 1 X X N, D 10¢ 0 0 10¢ 0 0 1 15¢ 0 15¢ 1 0 15¢ 0 [open] 1 1 X X 15¢ X X 15¢ 1 reuse states whenever Symbolic State Table possible © R.H. Katz Transparency No. 8-13
- 14. Contemporary Logic DesignVending Machine Finite State Machine DesignExample Step 4: State Encoding Present State Inputs Next State Output Q1 Q0 D N D1 D0 Open 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 1 1 X X X 0 1 0 0 0 1 0 0 1 1 0 0 1 0 1 1 0 1 1 X X X 1 0 0 0 1 0 0 0 1 1 1 0 1 0 1 1 0 1 1 X X X 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 X X X © R.H. Katz Transparency No. 8-14
- 15. Contemporary Logic Design Vending Machine Finite State Machine Design Example Step 5. Choose FFs for implementation D FF easiest to use Q1 Q1 Q1 Q1 Q0 Q1 Q0 Q1 Q0 DN DN DN N N N D D D Q0 Q0 Q0 K-map for D1 K-map for D0 K-map for Open Q1 D D1 D Q Q1 Q0 CLK RQ Q1 D1 = Q1 + D + Q0 N N reset N Q0 OPEN D0 = N Q0 + Q0 N + Q1 N + Q1 D Q0 N D0 D Q Q0 OPEN = Q1 Q0 Q1 CLK Q0 N RQ Q1 reset D 8 Gates © R.H. Katz Transparency No. 8-15
- 16. Contemporary Logic DesignVending Machine Finite State Machine DesignExampleStep 5. Choosing FF for Implementation J-K FF Present State Inputs Next State J1 K1 J0 K 0 Q1 Q0 D N D 1 D0 0 0 0 0 0 0 0 X 0 X 0 1 0 1 0 X 1 X 1 0 1 0 1 X 0 X 1 1 X X X X X X 0 1 0 0 0 1 0 X X 0 0 1 1 0 1 X X 1 1 0 1 1 1 X X 0 1 1 X X X X X X 1 0 0 0 1 0 X 0 0 X 0 1 1 1 X 0 1 X 1 0 1 1 X 0 1 X 1 1 X X X X X X 1 1 0 0 1 1 X 0 X 0 0 1 1 1 X 0 X 0 1 0 1 1 X 0 X 0 1 1 X X X X X X Remapped encoded state transition table © R.H. Katz Transparency No. 8-16
- 17. Contemporary Logic Design Vending Machine Finite State Machine Design Example Implementation: Q1 Q1 Q1 Q0 Q1 Q0DN DN J1 = D + Q0 N K1 = 0 N ND D J0 = Q0 N + Q1 D Q0 Q0 K-map for J1 K-map for K1 K0 = Q1 N Q1 Q1 Q1 Q0 Q1 Q0DN DN N N N Q0 J Q1 QD D D Q1 CLK K Q Q0 R Q0 Q0 N K-map for J0 K-map for K0 OPEN Q1 D Q0 J Q Q1 CLK Q0 KR Q N reset 7 Gates © R.H. Katz Transparency No. 8-17
- 18. Contemporary Logic DesignAlternative State Machine Representations Finite State Machine Design Why State Diagrams Are Not Enough Not flexible enough for describing very complex finite state machines Not suitable for gradual refinement of finite state machine Do not obviously describe an algorithm: that is, well specified sequence of actions based on input data algorithm = sequencing + data manipulation separation of control and data Gradual shift towards program-like representations: • Algorithmic State Machine (ASM) Notation • Hardware Description Languages (e.g., VHDL) © R.H. Katz Transparency No. 8-18
- 19. Contemporary Logic Design Alternative State Machine Representations Finite State Machine Design Algorithmic State Machine (ASM) Notation Three Primitive Elements: • State Box • Decision Box State Entry Path • Output Box State Code * ***State Machine in one state State State Box block per state time Name State ASM Output ListSingle Entry Point T F Block ConditionUnambiguous Exit Path for each combination Condition Output Box of inputs Box Conditional Output ListOutputs asserted high (.H) or low (.L); Immediate (I) Exits to other ASM Blocks or delayed til next clock © R.H. Katz Transparency No. 8-19
- 20. Contemporary Logic DesignAlternative State Machine Representations Finite State Machine Design ASM Notation Condition Boxes: Ordering has no effect on final outcome Equivalent ASM charts: A exits to B on (I0 • I1) else exit to C A 010 A 010 F F I0 I1 T T F F I1 I0 T T B C B C © R.H. Katz Transparency No. 8-20
- 21. Contemporary Logic DesignAlternative State Machine Representations Finite State Machine Design Example: Parity Checker Input X, Output Z Even 0 Nothing in output list implies Z not asserted Z asserted in State Odd F X Symbolic State Table: T Present Next Input State State Output Odd 1 F Even Even — H.Z T Even Odd — F Odd Odd A T Odd Even A F T X Encoded State Table: Present Next Input State State Output Trace paths to derive 0 0 0 0 state transition tables 1 0 1 0 0 1 1 1 1 1 0 1 © R.H. Katz Transparency No. 8-21
- 22. Contemporary Logic DesignAlternative State Machine Representations Finite State Machine Design ASM Chart for Vending Machine 0¢ 00 10¢ 10 T T D D F F F F N N T T 5¢ 01 15¢ 11 H.Open T F N Reset F T F T D 0¢ © R.H. Katz Transparency No. 8-22
- 23. Contemporary Logic DesignAlternative State Machine Representations Finite State Machine DesignHardware Description Languages: VHDL ENTITY parity_checker IS PORT ( x, clk: IN BIT; Interface Description z: OUT BIT); END parity_checker; Architectural Body ARCHITECTURE behavioral OF parity_checker IS BEGIN main: BLOCK (clk = ‘1’ and not clk’STABLE) TYPE state IS (Even, Odd); SIGNAL state_register: state := Even; Guard Expression BEGIN state_even: BLOCK ((state_register = Even) AND GUARD) BEGIN state_register <= Odd WHEN x = ‘1’ ELSE Even END BLOCK state_even; Determine New State BEGIN state_odd: BLOCK ((state_register = Odd) AND GUARD) BEGIN state_register <= Even WHEN x = ‘1’ ELSE Odd; END BLOCK state_odd; z <= ‘0’ WHEN state_register = Even ELSE Determine Outputs ‘1’ WHEN state_register = Odd; END BLOCK main; END behavioral; © R.H. Katz Transparency No. 8-23
- 24. Contemporary Logic Design Alternative State Machine Representations Finite State Machine Design ABEL Hardware Description Languagemodule parity test_vectors ([clk, RESET, X] -> [SREG])title odd parity checker state machine [0,1,.X.] -> [S0];u1 device p22v10; [.C.,0,1] -> [S1]; [.C.,0,1] -> [S0];"Input Pins [.C.,0,1] -> [S1]; clk, X, RESET pin 1, 2, 3; [.C.,0,0] -> [S1]; [.C.,0,1] -> [S0];"Output Pins [.C.,0,1] -> [S1]; Q, Z pin 21, 22; [.C.,0,0] -> [S1]; [.C.,0,0] -> [S1]; Q, Z istype pos,reg; [.C.,0,0] -> [S1]; end parity;"State registersSREG = [Q, Z];S0 = [0, 0]; " even number of 0sS1 = [1, 1]; " odd number of 0sequations [Q.ar, Z.ar] = RESET; "Reset to state S0state_diagram SREGstate S0: if X then S1 else S0;state S1: if X then S0 else S1; © R.H. Katz Transparency No. 8-24
- 25. Contemporary Logic Design Moore and Mealy Machine Design Procedure Finite State Machine Design Definitions Mealy Machine Xi Zk Outputs depend onInputs Combinational Outputs Logic for state AND inputs Outputs and Next State Input change causes an immediate output State change State Register Clock Feedback Asynchronous signals State Register Moore Machine Xi Comb. CombinationalInputs Logic for Logic for Outputs are function Outputs Next State solely of the current (Flip-flop Zk state Inputs) Outputs Clock Outputs change synchronously with state changes state feedback © R.H. Katz Transparency No. 8-25
- 26. Contemporary Logic Design Moore and Mealy Finite State Machine Design Machines State Diagram Equivalents N D + ResetMealy Reset/0 (N D + Reset)/0 Reset MooreMachine 0¢ 0¢ Machine [0] Reset/0 Reset N/0 N 5¢ 5¢ N D/0 D/0 ND D [0] N/0 N 10¢ 10¢ D/1 D N D/0 [0] ND N+D/1 N+D 15¢ 15¢ [1] Reset Reset/1 Outputs are associated Outputs are associated with Transitions with State © R.H. Katz Transparency No. 8-26
- 27. Contemporary Logic DesignMoore and Mealy Finite State Machine DesignMachines vs. Transitions States Mealy Machine typically has fewer states than Moore Machine for same output sequence 0 0 0/0 0Same I/O behavior:Assert a single output [0] 1/0 0/0whenever at least two 1’s 0 1 0 1have been received in a 1sequence. [0] 1/1 1Different # of states 2 [1] 1S0 00 S0 0 IN INS1 01 S1 1 Equivalent ASM Charts IN INS2 10 H.OUT H.OUT IN © R.H. Katz Transparency No. 8-27
- 28. Contemporary Logic DesignMoore and Mealy Finite State Machine DesignMachines Timing Behavior of Moore Machines Reverse engineer the following: X J Q A Input X C Output Z X KR Q A State A, B = Z B FFa Reset Clk X J Q Z X C KR Q B A FFb Reset Two Techniques for Reverse Engineering: • Ad Hoc: Try input combinations to derive transition table • Formal: Derive transition by analyzing the circuit © R.H. Katz Transparency No. 8-28
- 29. Contemporary Logic DesignMoore and Mealy Finite State Machine DesignMachines Ad Hoc Reverse Engineering Behavior in response to input sequence 1 0 1 0 1 0: 100XClkAZReset Reset X =1 X =0 X =1 X=0 X =1 X=0 X=0 AB = 00 AB = 00 AB = 11 AB = 11 AB = 10 AB = 10 AB = 01 AB = 00 A B X A+ B+ Z 0 0 0 ? ? 0 1 1 1 0 0 1 0 0 0 1 Partially Derived 1 ? ? 1 State Transition 1 0 0 1 0 0 Table 1 0 1 0 1 1 0 1 1 1 1 1 0 1 © R.H. Katz Transparency No. 8-29
- 30. Contemporary Logic DesignMoore and Mealy Finite State Machine DesignMachines Formal Reverse Engineering Derive transition table from next state and output combinational functions presented to the flipflops! Ja = X Ka = X • B Z=B Jb = X Kb = X xor A FF excitation equations for J-K flipflop: A+ = Ja • A + Ka • A = X • A + (X + B) • A B+ = Jb • B + Kb • B = X • B + (X • A + X • A) • B Next State K-Maps: AB 00 01 11 10 X 0 1 1 A+ State 00, Input 0 -> State 00 1 1 1 1 State 01, Input 1 -> State 11 AB X 00 01 11 10 0 1 B+ 1 1 1 1 © R.H. Katz Transparency No. 8-30
- 31. Contemporary Logic DesignMoore and Mealy Finite State Machine DesignMachines ASM Chart for the Mystery Moore Machine Complete S0 00 S3 11 H.Z 0 1 0 X X 1 S1 01 S2 10 H.Z 0 1 1 0 X X Note: All Outputs Associated With State Boxes No Separate Output Boxes — Intrinsic in Moore Machines © R.H. Katz Transparency No. 8-31
- 32. Contemporary Logic DesignMoore and Mealy Finite State Machine DesignMachines Engineering a Mealy Machine Reverse Clk A X A B D Q J Q DA A C B C X R Q KR Q Reset Reset A DA X X B B Z X X A Input X, Output Z, State A, B State register consists of D FF and J-K FF © R.H. Katz Transparency No. 8-32
- 33. Contemporary Logic Design Moore and Mealy Finite State Machine Design Machine Method Ad Hoc Signal Trace of Input Sequence 101011: 100X Note glitchesClk in Z!A Outputs valid atB following falling clock edgeZReset Reset X =1 X =0 X =1 X =0 X =1 X =1 AB =00 AB =00 AB =00 AB =01 AB =11 AB =10 AB =01 Z =0 Z =0 Z =0 Z =0 Z=1 Z =1 Z =0 A B X A+ B+ Z 0 0 0 0 1 0 Partially completed 1 0 0 0 state transition table 0 1 0 ? ? ? based on the signal 1 1 1 0 trace 1 0 0 ? ? ? 1 0 1 1 1 1 0 1 0 1 1 ? ? ? © R.H. Katz Transparency No. 8-33
- 34. Contemporary Logic DesignMoore and Mealy Finite State Machine DesignMachines Method Formal A+ = B • (A + X) = A • B + B • X B+ = Jb • B + Kb • B = (A xor X) • B + X • B =A•B•X + A•B•X + B•X Z =A•X + B•X Missing Transitions and Outputs: AB X 00 01 11 10 State 01, Input 0 -> State 00, Output 1 0 1 State 10, Input 0 -> State 00, Output 0 A+ State 11, Input 1 -> State 11, Output 1 1 1 1 AB X 00 01 11 10 0 1 B+ 1 1 1 1 AB X 00 01 11 10 0 1 1 Z 1 1 1 © R.H. Katz Transparency No. 8-34
- 35. Contemporary Logic DesignMoore and Mealy Finite State Machine DesignMachines ASM Chart for Mystery Mealy Machine S0 = 00, S1 = 01, S2 = 10, S3 = 11 S0 00 S2 10 0 1 X X 1 0 H. Z S1 01 S3 11 H. Z H.Z 0 1 1 X X 0 NOTE: Some Outputs in Output Boxes as well as State Boxes This is intrinsic in Mealy Machine implementation © R.H. Katz Transparency No. 8-35
- 36. Contemporary Logic DesignMoore and Mealy Finite State Machine DesignMachines Synchronous Mealy Machine Clock Xi Zk Inputs Combinational Outputs Logic for Outputs and Next State State Register Clock state feedback latched state AND outputs avoids glitchy outputs! © R.H. Katz Transparency No. 8-36
- 37. Contemporary Logic DesignFinite State Machine Word Finite State Machine DesignProblems Mapping English Language Description to Formal Specifications Four Case Studies: • Finite String Pattern Recognizer • Complex Counter with Decision Making • Traffic Light Controller • Digital Combination Lock We will use state diagrams and ASM Charts © R.H. Katz Transparency No. 8-37
- 38. Contemporary Logic DesignFinite State Machine Word Finite State Machine DesignProblems Finite String Pattern Recognizer A finite string recognizer has one input (X) and one output (Z). The output is asserted whenever the input sequence …010… has been observed, as long as the sequence 100 has never been seen. Step 1. Understanding the problem statement Sample input/output behavior: X: 00101010010… Z: 00010101000… X: 11011010010… Z: 00000001000… © R.H. Katz Transparency No. 8-38
- 39. Contemporary Logic DesignFinite State Machine Word Finite State Machine DesignProblems Finite String Recognizer Step 2. Draw State Diagrams/ASM Charts for the strings that must be recognized. I.e., 010 and 100. Reset S0 [0] Moore State Diagram 0 1 Reset signal places S1 S4 FSM in S0 [0] [0] 1 0 S2 S5 [0] [0] 0 0 0,1 S3 S6 Outputs 1 Loops in State [1] [0] © R.H. Katz Transparency No. 8-39
- 40. Contemporary Logic DesignFinite State Machine Word Finite State Machine DesignProblems Finite String Recognizer Exit conditions from state S3: have recognized …010 if next input is 0 then have …0100! if next input is 1 then have …0101 = …01 (state S2) Reset S0 [0] 0 1 S1 0 S4 [0] [0] 1 0 S2 S5 [0] [0] 0 0 1 0,1 S3 0 S6 [1] [0] © R.H. Katz Transparency No. 8-40
- 41. Contemporary Logic DesignFinite State Machine Word Finite State Machine DesignProblems Finite String Recognizer Exit conditions from S1: recognizes strings of form …0 (no 1 seen) loop back to S1 if input is 0 Exit conditions from S4: recognizes strings of form …1 (no 0 seen) loop back to S4 if input is 1 Reset S0 [0] 0 1 0 S1 0 S4 1 [0] [0] 1 0 S2 S5 [0] [0] 0 0 1 0,1 S3 0 S6 [1] [0] © R.H. Katz Transparency No. 8-41
- 42. Contemporary Logic DesignFinite State Machine Word Finite State Machine DesignProblems Finite String Recognizer S2, S5 with incomplete transitions S2 = …01; If next input is 1, then string could be prefix of (01)1(00) S4 handles just this case! S5 = …10; If next input is 1, then string could be prefix of (10)1(0) S2 handles just this case! Reset S0 [0] 0 1 0 S1 0 S4 1 [0] [0] Final State Diagram 1 1 0 S2 1 S5 [0] [0] 0 0 1 0,1 S3 0 S6 [1] [0] © R.H. Katz Transparency No. 8-42
- 43. Contemporary Logic Design Finite State Machine Word Finite State Machine Design Problems Finite String Recognizermodule string state_diagram SREGtitle 010/100 string recognizer state machine state S0: if X then S4 else S1; Josephine Engineer, Itty Bity Machines, Inc. state S1: if X then S2 else S1;u1 device p22v10; state S2: if X then S4 else S3; state S3: if X then S2 else S6;"Input Pins state S4: if X then S4 else S5; clk, X, RESET pin 1, 2, 3; state S5: if X then S2 else S6; state S6: goto S6;"Output Pins Q0, Q1, Q2, Z pin 19, 20, 21, 22; test_vectors ([clk, RESET, X] -> [Z] [0,1,.X.] -> [0]; Q0, Q1, Q2, Z istype pos,reg; [.C.,0,0] -> [0]; [.C.,0,0] -> [0];"State registers [.C.,0,1] -> [0];SREG = [Q0, Q1, Q2, Z]; [.C.,0,0] -> [1];S0 = [0,0,0,0]; " Reset state [.C.,0,1] -> [0];S1 = [0,0,1,0]; " strings of the form ...0 [.C.,0,0] -> [1];S2 = [0,1,0,0]; " strings of the form ...01 [.C.,0,1] -> [0];S3 = [0,1,1,1]; " strings of the form ...010 [.C.,0,0] -> [1];S4 = [1,0,0,0]; " strings of the form ...1 [.C.,0,0] -> [0];S5 = [1,0,1,0]; " strings of the form ...10 [.C.,0,1] -> [0];S6 = [1,1,0,0]; " strings of the form ...100 [.C.,0,0] -> [0]; end string;equations [Q0.ar, Q1.ar, Q2.ar, Z.ar] = RESET; "Reset to S0 ABEL Description © R.H. Katz Transparency No. 8-43
- 44. Contemporary Logic DesignFinite State Machine Word Finite State Machine DesignProblems Finite String Recognizer Review of Process: • Write down sample inputs and outputs to understand specification • Write down sequences of states and transitions for the sequences to be recognized • Add missing transitions; reuse states as much as possible • Verify I/O behavior of your state diagram to insure it functions like the specification © R.H. Katz Transparency No. 8-44
- 45. Contemporary Logic DesignFinite State Machine Word Finite State Machine DesignProblems Counter Complex A sync. 3 bit counter has a mode control M. When M = 0, the counter counts up in the binary sequence. When M = 1, the counter advances through the Gray code sequence. Binary: 000, 001, 010, 011, 100, 101, 110, 111 Gray: 000, 001, 011, 010, 110, 111, 101, 100 Valid I/O behavior: Mode Input M Current State Next State (Z2 Z1 Z0) 0 000 001 0 001 010 1 010 110 1 110 111 1 111 101 0 101 110 0 110 111 © R.H. Katz Transparency No. 8-45
- 46. Contemporary Logic DesignFinite State Machine Word Finite State Machine DesignProblems Counter Complex One state for each output combination Add appropriate arcs for the mode control S0 000 Reset S0 [000] M=0 S1 001 M=1 S1 H.Z 0 [001] 0 1 M=0 M M=1 M=1 S2 [010] S2 010 S3 011 H.Z 1 H.Z 1 M=1 M=0 H.Z 0 S3 0 M [011] M=0 1 1 M M=0 S6 110 0 S4 H.Z 2 S4 100 [100] H.Z 1 H.Z 2 M=1 M=0 1 S5 S7 111 M [101] H.Z 2 0 H.Z 1 M=0 H.Z 0 S5 101 M=1 S6 H.Z 2 H.Z 0 [110] 0 1 M M=1 M=0 0 1 S7 M [111] © R.H. Katz Transparency No. 8-46
- 47. Contemporary Logic Design Finite State Machine Word Finite State Machine Design Problems Counter Complexmodule countertitle combination binary/gray code upcounter Josephine Engineer, Itty Bity Machines, Inc.u1 device p22v10; state_diagram SREG"Input Pins state S0: goto S1; clk, M, RESET pin 1, 2, 3; state S1: if M then S3 else S2; state S2: if M then S6 else S3;"Output Pins state S3: if M then S2 else S4; Z0, Z1, Z2 pin 19, 20, 21; state S4: if M then S0 else S5; state S5: if M then S4 else S6; Z0, Z1, Z2 istype pos,reg; state S6: goto S7; state S7: if M then S5 else S0;"State registersSREG = [Z0, Z1, Z2]; test_vectors ([clk, RESET, M] -> [Z0, Z1, Z2])S0 = [0,0,0]; [0,1,.X.] -> [0,0,0];S1 = [0,0,1]; [.C.,0,0] -> [0,0,1];S2 = [0,1,0]; [.C.,0,0] -> [0,1,0];S3 = [0,1,1]; [.C.,0,1] -> [1,1,0];S4 = [1,0,0]; [.C.,0,1] -> [1,1,1];S5 = [1,0,1]; [.C.,0,1] -> [1,0,1];S6 = [1,1,0]; [.C.,0,0] -> [1,1,0];S7 = [1,1,1]; [.C.,0,0] -> [1,1,1]; end counter;equations [Z0.ar, Z1.ar, Z2.ar] = RESET; "Reset to state S0 ABEL Description © R.H. Katz Transparency No. 8-47
- 48. Contemporary Logic DesignFinite State Machine Word Finite State Machine DesignProblems Traffic Light Controller A busy highway is intersected by a little used farmroad. Detectors C sense the presence of cars waiting on the farmroad. With no car on farmroad, lights remain green in highway direction. If vehicle on farmroad, highway lights go from Green to Yellow to Red, allowing the farmroad lights to become green. These stay green only as long as a farmroad car is detected but never longer than a set interval. When these are met, farm lights transition from Green to Yellow to Red, allowing highway to return to green. Even if farmroad vehicles are waiting, highway gets at least a set interval as green. Assume you have an interval timer that generates a short time pulse (TS) and a long time pulse (TL) in response to a set (ST) signal. TS is to be used for timing yellow lights and TL for green lights. Farmroad C HL FL Highway Highway FL HL C Farmroad © R.H. Katz Transparency No. 8-48
- 49. Contemporary Logic DesignFinite State Machine Word Finite State Machine DesignProblems Traffic Light Controller Picture of Highway/Farmroad Intersection: Farmroad C HL FL Highway Highway FL HL C Farmroad © R.H. Katz Transparency No. 8-49
- 50. Contemporary Logic DesignFinite State Machine Word Finite State Machine DesignProblems Traffic Light Controller • Tabulation of Inputs and Outputs: Input Signal Description reset place FSM in initial state C detect vehicle on farmroad TS short time interval expired TL long time interval expired Output Signal Description HG, HY, HR assert green/yellow/red highway lights FG, FY, FR assert green/yellow/red farmroad lights ST start timing a short or long interval • Tabulation of Unique States: Some light configuration imply others State Description S0 Highway green (farmroad red) S1 Highway yellow (farmroad red) S2 Farmroad green (highway red) S3 Farmroad yellow (highway red) © R.H. Katz Transparency No. 8-50
- 51. Contemporary Logic DesignFinite State Machine Word Finite State Machine DesignProblems Traffic Light Controller Refinement of ASM Chart: Start with basic sequencing and outputs: S0 S3 H.HG H.HR H.FR H.FY S1 S2 H.HY H.HR H.FR H.FG © R.H. Katz Transparency No. 8-51
- 52. Contemporary Logic DesignFinite State Machine Word Finite State Machine DesignProblemsLight Controller Traffic Determine Exit Conditions for S0: Car waiting and Long Time Interval Expired- C • TL S0 S0 H.HG H.HG H.FR H.FR 0 0 TL TLÊ¥Ê C 1 1 0 C H.ST 1 H.ST S1 H.HY H.FR S1 H.HY H.FR Equivalent ASM Chart Fragments © R.H. Katz Transparency No. 8-52
- 53. Contemporary Logic DesignFinite State Machine Word Finite State Machine DesignProblems Traffic Light Controller S1 to S2 Transition: Set ST on exit from S0 Stay in S1 until TS asserted Similar situation for S3 to S4 transition S1 S2 H.HY H.ST H.HR H.FR H.FG 0 1 TS © R.H. Katz Transparency No. 8-53
- 54. Contemporary Logic DesignFinite State Machine Word Finite State Machine DesignProblems Traffic Light Controller S2 Exit Condition: no car waiting OR long time interval expired S0 S3 H.HG H.HR H.FR H.ST H.FY 0 1 0 TL ¥ C TS 1 H.ST H.ST S1 S2 H.HY H.ST H.HR H.FR H.FG 0 1 0 TS TL + C 1 Complete ASM Chart for Traffic Light Controller © R.H. Katz Transparency No. 8-54
- 55. Contemporary Logic DesignFinite State Machine Word Finite State Machine DesignProblemsLight Controller Traffic Compare with state diagram: TL + C Reset S0 TL¥C/ST TS/ST S0: HG TS S1 S3 S1: HY TS/ST TS S2: FG TL + C/ST S2 S3: FY TL ¥ C Advantages of State Charts: • Concentrates on paths and conditions for exiting a state • Exit conditions built up incrementally, later combined into single Boolean condition for exit • Easier to understand the design as an algorithm © R.H. Katz Transparency No. 8-55
- 56. Contemporary Logic Design Finite State Machine Word Finite State Machine Design Problems Traffic Light Controllermodule traffic HY = !Q0 & Q1;title traffic light FSM HR = (Q0 & !Q1) # (Q0 & Q1);u1 device p22v10; FG = Q0 & !Q1; FY = Q0 & Q1;"Input Pins FR = (!Q0 & !Q1) # (!Q0 & Q1); clk, C, RESET, TS, TLpin 1, 2, 3, 4, 5; state_diagram SREG state S0: if (TL & C) then S1 with ST = 1"Output Pins else S0 with ST = 0 Q0, Q1, HG, HY, HR, state S1: if TS then S2 with ST = 1 FG, FY, FR, ST else S1 with ST = 0pin 14, 15, 16, 17, 18, state S2: if (TL # !C) then S3 with ST = 1 19, 20, 21, 22; else S2 with ST = 0 state S3: if TS then S0 with ST = 1 Q0, Q1 istype pos,reg; else S3 with ST = 0 ST, HG, HY, HR, FG, FY, FR istype pos,com;test_vectors ([clk,RESET, C, TS, TL]->[SREG,HG,HY,HR,FG,FY,FR,ST])"State registers [.X., 1,.X.,.X.,.X.]->[ S0, 1, 0, 0, 0, 0, 1, 0];SREG = [Q0, Q1]; [.C., 0, 0, 0, 0]->[ S0, 1, 0, 0, 0, 0, 1, 0];S0 = [ 0, 0]; [.C., 0, 1, 0, 1]->[ S1, 0, 1, 0, 0, 0, 1, 0];S1 = [ 0, 1]; [.C., 0, 1, 0, 0]->[ S1, 0, 1, 0, 0, 0, 1, 0];S2 = [ 1, 0]; [.C., 0, 1, 1, 0]->[ S2, 0, 0, 1, 1, 0, 0, 0];S3 = [ 1, 1]; [.C., 0, 1, 0, 0]->[ S2, 0, 0, 1, 1, 0, 0, 0]; [.C., 0, 1, 0, 1]->[ S3, 0, 0, 1, 0, 1, 0, 0];equations [.C., 0, 1, 1, 0]->[ S0, 1, 0, 0, 0, 0, 1, 0]; [Q0.ar, Q1.ar] = RESET; end traffic; HG = !Q0 & !Q1; ABEL Description © R.H. Katz Transparency No. 8-56
- 57. Contemporary Logic DesignFinite State Machine Word Finite State Machine DesignProblems Digital Combination Lock "3 bit serial lock controls entry to locked room. Inputs are RESET, ENTER, 2 position switch for bit of key data. Locks generates an UNLOCK signal when key matches internal combination. ERROR light illuminated if key does not match combination. Sequence is: (1) Press RESET, (2) enter key bit, (3) Press ENTER, (4) repeat (2) & (3) two more times." Problem specification is incomplete: • how do you set the internal combination? • exactly when is the ERROR light asserted? Make reasonable assumptions: • hardwired into next state logic vs. stored in internal register • assert as soon as error is detected vs. wait until full combination has been entered Our design: registered combination plus error after full combination © R.H. Katz Transparency No. 8-57
- 58. Contemporary Logic DesignFinite State Machine Word Finite State Machine DesignProblems Digital Combination Lock Understanding the problem: draw a block diagram … RESET Operator Data ENTER UNLOCK KEY-IN Combination Lock FSM ERROR L0 Internal L1 Combination L2 Inputs: Outputs: Reset Unlock Enter Error Key-In L0, L1, L2 © R.H. Katz Transparency No. 8-58
- 59. Contemporary Logic DesignFinite State Machine Word Finite State Machine DesignProblems Digital Combination Lock Enumeration of states: what sequences lead to opening the door? error conditions on a second pass … START state plus three key COMParison states START START entered on RESET Exit START when ENTER is pressed 1 Reset 0 Enter 0 1 COMP0 N Continue on if Key-In matches L0 KI = L0 Y © R.H. Katz Transparency No. 8-59
- 60. Contemporary Logic DesignFinite State Machine Word Finite State Machine DesignProblems Digital Combination Lock COMP0 IDLE1 Path to unlock: N 0 KI = L 0 Enter Y 1 IDLE0 COMP2 Wait for Enter Key press 0 N Enter KI = L2 1 Y COMP1 DONE H.Unlock N 0 Compare Key-IN KI = L1 Reset Y 1 START © R.H. Katz Transparency No. 8-60
- 61. Contemporary Logic DesignFinite State Machine Word Finite State Machine DesignProblems Digital Combination Lock Now consider error paths Should follow a similar sequence as UNLOCK path, except asserting ERROR at the end: IDLE0 IDLE1 ERROR3 H.Error 0 0 0 Enter Enter Reset 1 1 1 ERROR1 ERROR2 START COMP0 error exits to IDLE0 COMP1 error exits to IDLE1 COMP2 error exits to ERROR3 © R.H. Katz Transparency No. 8-61
- 62. Contemporary Logic DesignFinite State Machine Word Finite State Machine Design Reset + EnterProblems Digital Combination Lock Reset Start Reset ¥ Enter Comp0 KI = L0 KI ≠L0 ¡ Enter Enter Idle0 Idle0 Enter Enter Comp1 Error1Equivalent State Diagram KI ≠L1 ¡ KI = L1 Enter Enter Idle1 Idle1 Enter Enter Comp2 Error2 ≠ KI ¡ L2 KI = L2 Reset Reset Done Error3 [Unlock] [Error] Reset Reset Start Start © R.H. Katz Transparency No. 8-62
- 63. Contemporary Logic Design Finite State Machine Word Finite State Machine Design Problems Combination Lockmodule locktitle comb. lock FSM equationsu1 device p22v10; [Q0.ar, Q1.ar, Q2.ar, Q3.ar] = RESET; UNLOCK = !Q0 & Q1 & Q2 & !Q3;"asserted in DONE"Input Pins ERROR = Q0 & !Q1 & Q2 & Q3; "asserted in ERROR3clk, RESET, ENTER, L0, L1, L2, KIpin 1, 2, 3, 4, 5, 6, 7; state_diagram SREG state START: if (RESET # !ENTER)"Output Pins then START else COMP0;Q0, Q1, Q2, Q3, UNLOCK, ERROR state COMP0: if (KI == L0) then IDLE0 else IDLE0p;pin 16, 17, 18, 19, 14, 15; state IDLE0: if (!ENTER) then IDLE0 else COMP1; state COMP1: if (KI == L1) then IDLE1 else IDLE1p;Q0, Q1, Q2, Q3 istype pos,reg;state IDLE1: if (!ENTER) then IDLE1 else COMP2;UNLOCK, ERROR istype pos,com;state COMP2: if (KI == L2) then DONE else ERROR3; state DONE: if (!RESET) then DONE else START;"State registers state IDLE0p:if (!ENTER) then IDLE0p else ERROR1;SREG = [Q0, Q1, Q2, Q3]; state ERROR1:goto IDLE1p;START = [ 0, 0, 0, 0]; state IDLE1p:if (!ENTER) then IDLE1p else ERROR2;COMP0 = [ 0, 0, 0, 1]; state ERROR2:goto ERROR3;IDLE0 = [ 0, 0, 1, 0]; state ERROR3:if (!RESET) then ERROR3 else START;COMP1 = [ 0, 0, 1, 1];IDLE1 = [ 0, 1, 0, 0]; test_vectorsCOMP2 = [ 0, 1, 0, 1];DONE = [ 0, 1, 1, 0]; end lock;IDLE0p = [ 0, 1, 1, 1];ERROR1 = [ 1, 0, 0, 0];IDLE1p = [ 1, 0, 0, 1];ERROR2 = [ 1, 0, 1, 0];ERROR3 = [ 1, 0, 1, 1]; © R.H. Katz Transparency No. 8-63
- 64. Contemporary Logic DesignChapter Review Finite State Machine DesignBasic Timing Behavior an FSM • when are inputs sampled, next state/outputs transition and stabilize • Moore and Mealy (Async and Sync) machine organizations outputs = F(state) vs. outputs = F(state, inputs)First Two Steps of the Six Step Procedure for FSM Design • understanding the problem • abstract representation of the FSMAbstract Representations of an FSM • ASM Charts, Hardware Description LanguagesWord Problems • understand I/O behavior; draw diagrams • enumerate states for the "goal"; expand with error conditions • reuse states whenever possible © R.H. Katz Transparency No. 8-64

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