1. Investigation on FPGA based Passive Anti-Islanding Protection
Schemes for Grid Interfaced Distributed Generation System
Satabdy Jena, Gayadhar Panda and Rangababu Peesapati
Presented by:
Dr. Rangababu Peesapati
Assistant Professor
National Institute of Technology Meghalaya
India.
2. Outline
Introduction
Topology of the system
DG Inverter Control
DG Islanding & Anti-islanding protection schemes for grid connected inverter
system
Simulation Study
HIL co-simulation of grid-connected inverter system
Conclusion
Future Scope
References
211/13/2016 Investigation on FPGA based Passive Anti-Islanding Protection Schemes for Grid Interfaced Distributed Generation System
3. Introduction
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• Conventional resources are under immense pressure due to increasing population
and increasing demand.
• Renewable energy resources have emerged as the most promising alternative.
• Grid Interfaced Distributed Generation (DG) possess the potential to meet local
demand of power as well as feed the excess power to the grid.
• Safety of critical loads, devices and personnel: Reliable tripping is required.
• Anti-islanding detection.
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Fig.1. Topology of system
MPPT PWM
SPWM MAF-
PLL
Modulating
Signal
Generation
DC-
LINK
PI
PV
+-
V*dc
vdc
3-ф
Inverter
Filter
Inductance
Isolation
Transformer
ia,b,c
ua,b,c
iq*
id*
iq
uq
Grid
abc
dq
ud* uq*
DC/DC
Boost
Converter
LfRf
Cf LtRt
ϴ ϴ
Reference
Signal
Generation
md
q
Xilinx System Generator
ipv
vpv LOAD
Anti-islanding
Protection
B2B1
TripTrip
Trip
f
PCC
id
iq
+
+
-
-
PI
PI
id
ud
ωL
+
+
+
+
+
-
ωL
Decoupling
Technique
MATLAB/Simulink
FPGA ML605
Evaluation platform
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Moving Average Filter (MAF) : linear-phase finite impulse response filter
• Easy to realize in practice
• Effective in terms of computational burden
• 𝐺 𝑀𝐴𝐹 =
1
𝑁
1−𝑧−𝑁
1−𝑧−1
* *u * K (i i ) K (i i )dt ωLi u
q p q q i q q d q
* *u * K (i i ) K (i i )dt ωLi u
d p d d i d d q d
Decoupling Control : Control of d-q axes currents
DG Inverter Control
ωf
PI
+ ʃ
0
ω'
θ
-+abc
dq
uq
+
+
Z-1
Z-N
1
N+
-
MAF
K
f
ua,b,c
Fig.2. MAF-Phase Locked Loop
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DG Islanding
Islanding: DG continues to supply power to a location even though the electric utility is not present.
Types-
• Intentional
• Unintentional
Problems-
• Safety concerns
• End-user equipment damage
• Degradation of electrical components
• Out of phase reclosing of DG
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Remote Protection Schemes: Active and Passive.
Employed Schemes-
DC-Link protection
Over and Under frequency protection
Rate of change of frequency
The FPGA implementation enables for the automation of
the grid.
>
>
>
OR
OR
+-
(a)
(b)
(c)
˂
˂
z-1
d
dt β
vdc
vdc,high
vdc,low
flow
fhigh
f
f
Trip
Trip
Trip
Fig.3. AI Protection Schemes
Investigation on FPGA based Passive Anti-Islanding Protection Schemes for Grid Interfaced Distributed Generation System
Anti islanding Protection Schemes
8. The following cases were investigated :
• Loads less than the PV generation
• Resistive (P = 50 kW)
• Inductive (P = 50 kW, Q = 10 kVAr)
• Capacitive (P = 50 kW, Q = 10 kVAr)
• Loads greater than the PV generation
• Resistive (P = 110 kW)
• Inductive (P = 110 kW, Q = 50 kVAr)
• Capacitive (P = 110 kW, Q = 50 kVAr)
• Loads equal to PV generation
• Resistive (P = 80 kW)
• Inductive (P = 80 kW, Q = 50 kVAr)
• Capacitive (P = 80 kW, Q = 50 kVAr)
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Simulation Study
9. System parameters Value System parameters Value
Series connected modules 7 DC Link voltage 750 V
Parallel connected
modules
40 Filter inductance and resistance 1 mH, 3 mΩ
MPP Voltage 54.7 V Grid inductance and resistance 16 mH, 0.8929 Ω
MPP Current 5.58 A Transformer inductance and
resistance
0.06 mH, 0.002 mΩ
Open-circuit voltage 64.2 V Inverter switching frequency 5 .5 kHz
Short-circuit current 5.96 A Boost switching frequency 5 kHz
Maximum PV power
(STC, S = 1000 W/m2
)
85 kW Grid voltage 400 V
DC Link capacitor 5000 μF Grid frequency 50 Hz
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Table 1. System parameters
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Local loads less than PV generation: (a) Resistive load (P=50 kW)
(b) Inductive load (P=50 kW, Q=10 kVAr)
Fig.4. Power exchange Fig.5. Relay response
Fig.6. Power exchange Fig.7. Relay response
Investigation on FPGA based Passive Anti-Islanding Protection Schemes for Grid Interfaced Distributed Generation System
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(c) Capacitive load (P=50 kW, Q=10 kVAr)
Fig.9. Relay response
Fig.8. Power Exchange
Fig.10. Frequency deviation Fig.11. Voltage deviation
Investigation on FPGA based Passive Anti-Islanding Protection Schemes for Grid Interfaced Distributed Generation System
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Local loads greater than PV generation: (a) Resistive load (P=110 kW)
(b) Inductive load (P=110 kW, Q=50 kVAr)
Fig.12. Power Exchange Fig.13. Relay response
Fig.15. Relay responseFig.14. Power Exchange
Investigation on FPGA based Passive Anti-Islanding Protection Schemes for Grid Interfaced Distributed Generation System
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(c) Capacitive load (P=110 kW, Q=50 kVAr)
Fig.16. Power Exchange Fig.17. Relay Response
Fig.18. Frequency deviation
Fig.19. Voltage deviation
Investigation on FPGA based Passive Anti-Islanding Protection Schemes for Grid Interfaced Distributed Generation System
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Local loads equal to PV generation: (a) Active load (P=80 kW)
(b) Inductive load (P=80 kW, Q=50 kVAr)
Fig.20. Power Exchange Fig.21. Relay Response
Fig.22. Power Exchange Fig.23. Relay Response
Investigation on FPGA based Passive Anti-Islanding Protection Schemes for Grid Interfaced Distributed Generation System
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(c) Capacitive load (P=80 kW, Q=50 kVAr)
Fig.25. Relay ResponseFig.24. Power Exchange
Fig.26. Frequency deviation
Fig.27. Voltage deviation
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Table 2. Comparison of Relay Response
Gen-load
Relay
Load less than PV power Load more than PV power Load equals PV power
Resistive
(Relay
Time (s))
Inductive
(Relay
Time (s))
Capacitive
(Relay
Time (s))
Resistive
(Relay
Time (s))
Inductive
(Relay
Time (s))
Capacitive
(Relay
Time (s))
Resistive
(Relay
Time (s))
Inductive
(Relay
Time (s))
Capacitive
(Relay Time
(s))
Over-
Frequency
No
Trip
0.0792 No
Trip
0.1107 0.0732 0.0438 0.0764 0.0735 No
Trip
Under-
Frequency
0.3407 No
Trip
0.177 0.3417 No
Trip
No
Trip
0.3774 No
Trip
0.1077
ROCOF 0.0121 0.0864 0.0293 0.0296 0.0315 0.0293 0.0429 0.0486 0.0084
DC-Link 0.07123 0.0132 0.0295 0.0297 0.0317 0.0295 0.0431 0.0487 0.0085
Investigation on FPGA based Passive Anti-Islanding Protection Schemes for Grid Interfaced Distributed Generation System
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Simulink as FPGA design tool is easy to use as there is no need of learning HDL.
Hardware co-simulation is achieved by Xilinx System Generator which puts hardware into Simulink
design.
It enables automatic data exchange.
It supports FPGA chips with JTAG programming.
HIL Co-simulation study
Fig.28. FPGA building blocks Fig.29. Configuration of each logic block
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HIL Implementation
Fig.30. Ani-islanding protection schemes in XSG
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Fig.31. PLL, Reference Signal generation and Voltage controller in XSG
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Fig.32. Behavioral simulation for (a) PLL (b) Current Controller (c) SPWM
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Fig.34. Experimental Testbed
• ML605
• XILINX 14.2
• Matlab 2012a
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Fig.35. Relay response for load demand more than PV generation (a) Resistive (b) Inductive load
Fig.36. Relay response for load demand less than PV generation (a) Resistive (b) Inductive load
(a)
(a) (b)
(b)
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Fig.37. Relay response for load demand equal to PV generation (a) Resistive (b) Capacitive load
(a) (b)
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Gen-load
Relay
Load less than PV power Load more than PV power Load equals PV power
Resistive
(Relay
Time (s))
Inductive
(Relay
Time (s))
Capacitive
(Relay
Time (s))
Resistive
(Relay
Time
(s))
Inductive
(Relay
Time (s))
Capacitive
(Relay
Time (s))
Resistive
(Relay
Time (s))
Inductive
(Relay
Time (s))
Capacitive
(Relay
Time (s))
Over-
Frequency
No
Trip
0.3448 No
Trip
0.1107 0.0655 0.077 0.0942 0.0977 No
Trip
Under-
Frequency
0.381 0.069 0.0718 0.3417 0.381 No
Trip
No
Trip
0.4963 0.1086
ROCOF 0.0256 0.03 0.0293 0.02 0.0267 0.02 0.02 0.03 0.003
DC-Link 0.0655 0.0224 0.0295 0.0401 0.03 0.06 0.0401 0.0501 0.0501
Table 4. Comparison of Relay Response in HIL
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The synchronization of DG inverter with the grid was made possible by the help
of Decoupling Control and MAF-PLL.
The performance of the DG inverter control and the anti-islanding detection
schemes was studied under various conditions in time-domain simulation using
Matlab/Simulink.
The effectiveness of the proposed controllers and islanding detection schemes was
validated by developing a hardware-in-loop simulation using XSG.
The HIL response of the employed schemes were found to conform to its
simulation counterpart.
Conclusion
27. Application of signal processing techniques for detection of islanding.
Real time implementation of the proposed system.
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Future Scope
28. References
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30. Thank you
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